mirror of https://github.com/acidanthera/audk.git
253 lines
9.2 KiB
C
253 lines
9.2 KiB
C
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/*++
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Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Module Name:
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VlvCommonDefinitions.h
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Abstract:
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Macros to simplify and abstract the interface to PCI configuration.
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--*/
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///
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/// PCI CONFIGURATION MAP REGISTER OFFSETS
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///
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#ifndef PCI_VID
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#define PCI_VID 0x0000 ///< Vendor ID Register
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#define PCI_DID 0x0002 ///< Device ID Register
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#define PCI_CMD 0x0004 ///< PCI Command Register
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#define PCI_STS 0x0006 ///< PCI Status Register
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#define PCI_RID 0x0008 ///< Revision ID Register
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#define PCI_IFT 0x0009 ///< Interface Type
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#define PCI_SCC 0x000A ///< Sub Class Code Register
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#define PCI_BCC 0x000B ///< Base Class Code Register
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#define PCI_CLS 0x000C ///< Cache Line Size
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#define PCI_PMLT 0x000D ///< Primary Master Latency Timer
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#define PCI_HDR 0x000E ///< Header Type Register
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#define PCI_BIST 0x000F ///< Built in Self Test Register
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#define PCI_BAR0 0x0010 ///< Base Address Register 0
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#define PCI_BAR1 0x0014 ///< Base Address Register 1
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#define PCI_BAR2 0x0018 ///< Base Address Register 2
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#define PCI_PBUS 0x0018 ///< Primary Bus Number Register
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#define PCI_SBUS 0x0019 ///< Secondary Bus Number Register
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#define PCI_SUBUS 0x001A ///< Subordinate Bus Number Register
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#define PCI_SMLT 0x001B ///< Secondary Master Latency Timer
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#define PCI_BAR3 0x001C ///< Base Address Register 3
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#define PCI_IOBASE 0x001C ///< I/O base Register
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#define PCI_IOLIMIT 0x001D ///< I/O Limit Register
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#define PCI_SECSTATUS 0x001E ///< Secondary Status Register
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#define PCI_BAR4 0x0020 ///< Base Address Register 4
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#define PCI_MEMBASE 0x0020 ///< Memory Base Register
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#define PCI_MEMLIMIT 0x0022 ///< Memory Limit Register
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#define PCI_BAR5 0x0024 ///< Base Address Register 5
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#define PCI_PRE_MEMBASE 0x0024 ///< Prefetchable memory Base register
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#define PCI_PRE_MEMLIMIT 0x0026 ///< Prefetchable memory Limit register
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#define PCI_PRE_MEMBASE_U 0x0028 ///< Prefetchable memory base upper 32 bits
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#define PCI_PRE_MEMLIMIT_U 0x002C ///< Prefetchable memory limit upper 32 bits
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#define PCI_SVID 0x002C ///< Subsystem Vendor ID
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#define PCI_SID 0x002E ///< Subsystem ID
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#define PCI_IOBASE_U 0x0030 ///< I/O base Upper Register
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#define PCI_IOLIMIT_U 0x0032 ///< I/O Limit Upper Register
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#define PCI_CAPP 0x0034 ///< Capabilities Pointer
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#define PCI_EROM 0x0038 ///< Expansion ROM Base Address
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#define PCI_INTLINE 0x003C ///< Interrupt Line Register
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#define PCI_INTPIN 0x003D ///< Interrupt Pin Register
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#define PCI_MAXGNT 0x003E ///< Max Grant Register
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#define PCI_BRIDGE_CNTL 0x003E ///< Bridge Control Register
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#define PCI_MAXLAT 0x003F ///< Max Latency Register
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#endif
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//
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// Bit Difinitions
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//
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#ifndef BIT0
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#define BIT0 0x0001
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#define BIT1 0x0002
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#define BIT2 0x0004
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#define BIT3 0x0008
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#define BIT4 0x0010
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#define BIT5 0x0020
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#define BIT6 0x0040
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#define BIT7 0x0080
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#define BIT8 0x0100
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#define BIT9 0x0200
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#define BIT10 0x0400
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#define BIT11 0x0800
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#define BIT12 0x1000
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#define BIT13 0x2000
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#define BIT14 0x4000
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#define BIT15 0x8000
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#define BIT16 0x00010000
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#define BIT17 0x00020000
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#define BIT18 0x00040000
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#define BIT19 0x00080000
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#define BIT20 0x00100000
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#define BIT21 0x00200000
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#define BIT22 0x00400000
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#define BIT23 0x00800000
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#define BIT24 0x01000000
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#define BIT25 0x02000000
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#define BIT26 0x04000000
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#define BIT27 0x08000000
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#define BIT28 0x10000000
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#define BIT29 0x20000000
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#define BIT30 0x40000000
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#define BIT31 0x80000000
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#endif
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#ifndef _PCIACCESS_H_INCLUDED_
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#define _PCIACCESS_H_INCLUDED_
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#ifndef PCI_EXPRESS_BASE_ADDRESS
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#define PCI_EXPRESS_BASE_ADDRESS 0xE0000000
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#endif
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#ifndef MmPciAddress
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#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
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( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \
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(UINTN)(Bus << 20) + \
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(UINTN)(Device << 15) + \
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(UINTN)(Function << 12) + \
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(UINTN)(Register) \
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)
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#endif
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//
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// UINT64
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//
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#define MmPci64Ptr( Segment, Bus, Device, Function, Register ) \
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( (volatile UINT64 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
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#define MmPci64( Segment, Bus, Device, Function, Register ) \
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*MmPci64Ptr( Segment, Bus, Device, Function, Register )
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#define MmPci64Or( Segment, Bus, Device, Function, Register, OrData ) \
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MmPci64( Segment, Bus, Device, Function, Register ) = \
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(UINT64) ( \
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MmPci64( Segment, Bus, Device, Function, Register ) | \
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(UINT64)(OrData) \
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)
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#define MmPci64And( Segment, Bus, Device, Function, Register, AndData ) \
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MmPci64( Segment, Bus, Device, Function, Register ) = \
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(UINT64) ( \
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MmPci64( Segment, Bus, Device, Function, Register ) & \
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(UINT64)(AndData) \
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)
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#define MmPci64AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
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MmPci64( Segment, Bus, Device, Function, Register ) = \
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(UINT64) ( \
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( MmPci64( Segment, Bus, Device, Function, Register ) & \
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(UINT64)(AndData) \
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) | \
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(UINT64)(OrData) \
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)
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//
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// UINT32
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//
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#define MmPci32Ptr( Segment, Bus, Device, Function, Register ) \
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( (volatile UINT32 *) MmPciAddress( Segment, Bus, Device, Function, Register ) )
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#define MmPci32( Segment, Bus, Device, Function, Register ) \
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*MmPci32Ptr( Segment, Bus, Device, Function, Register )
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#define MmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \
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MmPci32( Segment, Bus, Device, Function, Register ) = \
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(UINT32) ( \
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MmPci32( Segment, Bus, Device, Function, Register ) | \
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(UINT32)(OrData) \
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)
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#define MmPci32And( Segment, Bus, Device, Function, Register, AndData ) \
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MmPci32( Segment, Bus, Device, Function, Register ) = \
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(UINT32) ( \
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MmPci32( Segment, Bus, Device, Function, Register ) & \
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(UINT32)(AndData) \
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)
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#define MmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
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MmPci32( Segment, Bus, Device, Function, Register ) = \
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(UINT32) ( \
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( MmPci32( Segment, Bus, Device, Function, Register ) & \
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(UINT32)(AndData) \
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) | \
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(UINT32)(OrData) \
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)
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//
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// UINT16
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//
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#define MmPci16Ptr( Segment, Bus, Device, Function, Register ) \
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( (volatile UINT16 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
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#define MmPci16( Segment, Bus, Device, Function, Register ) \
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*MmPci16Ptr( Segment, Bus, Device, Function, Register )
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#define MmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \
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MmPci16( Segment, Bus, Device, Function, Register ) = \
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(UINT16) ( \
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MmPci16( Segment, Bus, Device, Function, Register ) | \
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(UINT16)(OrData) \
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)
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#define MmPci16And( Segment, Bus, Device, Function, Register, AndData ) \
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MmPci16( Segment, Bus, Device, Function, Register ) = \
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(UINT16) ( \
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MmPci16( Segment, Bus, Device, Function, Register ) & \
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(UINT16)(AndData) \
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)
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#define MmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
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MmPci16( Segment, Bus, Device, Function, Register ) = \
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(UINT16) ( \
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( MmPci16( Segment, Bus, Device, Function, Register ) & \
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(UINT16)(AndData) \
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) | \
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(UINT16)(OrData) \
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)
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//
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// UINT8
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//
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#define MmPci8Ptr( Segment, Bus, Device, Function, Register ) \
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( (volatile UINT8 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
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#define MmPci8( Segment, Bus, Device, Function, Register ) \
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*MmPci8Ptr( Segment, Bus, Device, Function, Register )
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#define MmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \
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MmPci8( Segment, Bus, Device, Function, Register ) = \
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(UINT8) ( \
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MmPci8( Segment, Bus, Device, Function, Register ) | \
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(UINT8)(OrData) \
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)
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#define MmPci8And( Segment, Bus, Device, Function, Register, AndData ) \
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MmPci8( Segment, Bus, Device, Function, Register ) = \
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(UINT8) ( \
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MmPci8( Segment, Bus, Device, Function, Register ) & \
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(UINT8)(AndData) \
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)
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#define MmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
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MmPci8( Segment, Bus, Device, Function, Register ) = \
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(UINT8) ( \
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( MmPci8( Segment, Bus, Device, Function, Register ) & \
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(UINT8)(AndData) \
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) | \
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(UINT8)(OrData) \
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)
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#endif
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