mirror of https://github.com/acidanthera/audk.git
6fdd1c13a7
https://bugzilla.tianocore.org/show_bug.cgi?id=3525 After PciSegmentLib using Dynamic PCD for Pcie base address such long delay found in FSP. The root cause is some of the PCD service PPIs not shadowed to memory and flash cache may have been disabled in NotifyPhase stage. Solution is to shadow all PCD service PPIs to memory. Signed-off-by: GregX Yeh <gregx.yeh@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> |
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| Application | ||
| Bus | ||
| Core | ||
| Include | ||
| Library | ||
| Logo | ||
| Test | ||
| Universal | ||
| MdeModulePkg.ci.yaml | ||
| MdeModulePkg.dec | ||
| MdeModulePkg.dsc | ||
| MdeModulePkg.uni | ||
| MdeModulePkgExtra.uni | ||