mirror of https://github.com/acidanthera/audk.git
299 lines
11 KiB
NASM
299 lines
11 KiB
NASM
//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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INCLUDE AsmMacroExport.inc
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PRESERVE8
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DC_ON EQU ( 0x1:SHL:2 )
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IC_ON EQU ( 0x1:SHL:12 )
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CTRL_M_BIT EQU (1 << 0)
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CTRL_C_BIT EQU (1 << 2)
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CTRL_B_BIT EQU (1 << 7)
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CTRL_I_BIT EQU (1 << 12)
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RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
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bx lr
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RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
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bx lr
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RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA
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mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU
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mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor
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bx lr
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RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA
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mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU
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bx lr
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RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA
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mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
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bx lr
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RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
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bx lr
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RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
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bx lr
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RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c10, 2 ; Clean this line
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bx lr
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RVCT_ASM_EXPORT ArmInvalidateInstructionCache
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mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
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isb
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bx LR
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RVCT_ASM_EXPORT ArmEnableMmu
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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dsb
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isb
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bx LR
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RVCT_ASM_EXPORT ArmDisableMmu
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
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mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
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dsb
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isb
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bx LR
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RVCT_ASM_EXPORT ArmDisableCachesAndMmu
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mrc p15, 0, r0, c1, c0, 0 ; Get control register
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bic r0, r0, #CTRL_M_BIT ; Disable MMU
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bic r0, r0, #CTRL_C_BIT ; Disable D Cache
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bic r0, r0, #CTRL_I_BIT ; Disable I Cache
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mcr p15, 0, r0, c1, c0, 0 ; Write control register
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dsb
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isb
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bx LR
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RVCT_ASM_EXPORT ArmMmuEnabled
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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and R0,R0,#1
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bx LR
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RVCT_ASM_EXPORT ArmEnableDataCache
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ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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dsb
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isb
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bx LR
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RVCT_ASM_EXPORT ArmDisableDataCache
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ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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dsb
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isb
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bx LR
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RVCT_ASM_EXPORT ArmEnableInstructionCache
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ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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dsb
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isb
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bx LR
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RVCT_ASM_EXPORT ArmDisableInstructionCache
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ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
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mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
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BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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RVCT_ASM_EXPORT ArmEnableSWPInstruction
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000400
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mcr p15, 0, r0, c1, c0, 0
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isb
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bx LR
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RVCT_ASM_EXPORT ArmEnableBranchPrediction
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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orr r0, r0, #0x00000800 ;
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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dsb
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isb
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bx LR
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RVCT_ASM_EXPORT ArmDisableBranchPrediction
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00000800 ;
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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dsb
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isb
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bx LR
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RVCT_ASM_EXPORT ArmSetLowVectors
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00002000 ; clear V bit
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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RVCT_ASM_EXPORT ArmSetHighVectors
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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orr r0, r0, #0x00002000 ; Set V bit
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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RVCT_ASM_EXPORT ArmV7AllDataCachesOperation
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stmfd SP!,{r4-r12, LR}
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mov R1, R0 ; Save Function call in R1
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mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
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ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
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mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
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beq Finished
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mov R10, #0
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Loop1
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add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
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mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
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and R12, R12, #7 ; get those 3 bits alone
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cmp R12, #2
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blt Skip ; no cache or only instruction cache at this level
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mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
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isb ; isb to sync the change to the CacheSizeID reg
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mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
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and R2, R12, #&7 ; extract the line length field
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add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
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ldr R4, =0x3FF
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ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
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clz R5, R4 ; R5 is the bit position of the way size increment
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ldr R7, =0x00007FFF
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ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
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Loop2
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mov R9, R4 ; R9 working copy of the max way size (right aligned)
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Loop3
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orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
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orr R0, R0, R7, LSL R2 ; factor in the index number
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blx R1
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subs R9, R9, #1 ; decrement the way number
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bge Loop3
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subs R7, R7, #1 ; decrement the index
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bge Loop2
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Skip
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add R10, R10, #2 ; increment the cache number
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cmp R3, R10
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bgt Loop1
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Finished
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dsb
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ldmfd SP!, {r4-r12, lr}
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bx LR
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RVCT_ASM_EXPORT ArmDataMemoryBarrier
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dmb
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bx LR
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RVCT_ASM_EXPORT ArmDataSynchronizationBarrier
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dsb
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bx LR
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RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier
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isb
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bx LR
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RVCT_ASM_EXPORT ArmReadVBar
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// Set the Address of the Vector Table in the VBAR register
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mrc p15, 0, r0, c12, c0, 0
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bx lr
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RVCT_ASM_EXPORT ArmWriteVBar
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// Set the Address of the Vector Table in the VBAR register
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mcr p15, 0, r0, c12, c0, 0
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// Ensure the SCTLR.V bit is clear
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mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00002000 ; clear V bit
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mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
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isb
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bx lr
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RVCT_ASM_EXPORT ArmEnableVFP
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// Read CPACR (Coprocessor Access Control Register)
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mrc p15, 0, r0, c1, c0, 2
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// Enable VPF access (Full Access to CP10, CP11) (V* instructions)
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orr r0, r0, #0x00f00000
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// Write back CPACR (Coprocessor Access Control Register)
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mcr p15, 0, r0, c1, c0, 2
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isb
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// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
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mov r0, #0x40000000
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mcr p10,#0x7,r0,c8,c0,#0
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bx lr
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RVCT_ASM_EXPORT ArmCallWFI
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wfi
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bx lr
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//Note: Return 0 in Uniprocessor implementation
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RVCT_ASM_EXPORT ArmReadCbar
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mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
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bx lr
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RVCT_ASM_EXPORT ArmReadMpidr
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mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
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bx lr
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RVCT_ASM_EXPORT ArmReadTpidrurw
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mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
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bx lr
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RVCT_ASM_EXPORT ArmWriteTpidrurw
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mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
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bx lr
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RVCT_ASM_EXPORT ArmIsArchTimerImplemented
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mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1
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and r0, r0, #0x000F0000
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bx lr
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RVCT_ASM_EXPORT ArmReadIdPfr1
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mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register
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bx lr
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END
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