mirror of https://github.com/acidanthera/audk.git
e6042aec1b
While RISC-V hart is trapped into S-Mode, the S-Mode interrupt CSR (SIE) is disabled by RISC-V hart. However the (SIE) is enabled again by RestoreTPL, this causes the second S-Mode trap is triggered by the machine mode (M-Mode)timer interrupt redirection. The SRET instruction clear Supervisor Previous Privilege (SPP) to zero (User mode) in the second S-Mode interrupt according to the RISC-V spec. Above brings hart to the user mode (U-Mode) when execute SRET in the nested S-Mode interrupt handler because SPP is set to User Mode in the second interrupt. Afterward, system runs in U-Mode and any accesses to S-Mode CSR causes the invalid instruction exception. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Abner Chang <abner.chang@hpe.com> Acked-by: Liming Gao <liming.gao@intel.com> |
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| .. | ||
| CpuBreakpoint.c | ||
| CpuPause.c | ||
| DisableInterrupts.c | ||
| EnableInterrupts.c | ||
| FlushCache.S | ||
| GetInterruptState.c | ||
| InternalSwitchStack.c | ||
| RiscVCpuBreakpoint.S | ||
| RiscVCpuPause.S | ||
| RiscVInterrupt.S | ||
| RiscVSetJumpLongJump.S | ||