mirror of https://github.com/acidanthera/audk.git
140 lines
2.8 KiB
NASM
140 lines
2.8 KiB
NASM
//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
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//
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// All rights reserved. This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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EXPORT Cp15IdCode
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EXPORT Cp15CacheInfo
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EXPORT ArmEnableInterrupts
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EXPORT ArmDisableInterrupts
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EXPORT ArmGetInterruptState
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EXPORT ArmInvalidateTlb
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EXPORT ArmSetTranslationTableBaseAddress
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EXPORT ArmGetTranslationTableBaseAddress
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EXPORT ArmSetDomainAccessControl
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EXPORT CPSRMaskInsert
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EXPORT CPSRRead
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AREA ArmLibSupport, CODE, READONLY
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Cp15IdCode
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DSB
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ISB
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mrc p15,0,R0,c0,c0,0
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DSB
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ISB
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bx LR
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Cp15CacheInfo
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DSB
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ISB
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mrc p15,0,R0,c0,c0,1
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DSB
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ISB
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bx LR
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ArmEnableInterrupts
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DSB
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ISB
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mrs R0,CPSR
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bic R0,R0,#0x80 ;Enable IRQ interrupts
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msr CPSR_c,R0
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DSB
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ISB
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bx LR
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ArmDisableInterrupts
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DSB
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ISB
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mrs R0,CPSR
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orr R1,R0,#0x80 ;Disable IRQ interrupts
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msr CPSR_c,R1
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tst R0,#0x80
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moveq R0,#1
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movne R0,#0
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DSB
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ISB
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bx LR
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ArmGetInterruptState
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DSB
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ISB
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mrs R0,CPSR
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tst R0,#0x80 ;Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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DSB
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ISB
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bx LR
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ArmInvalidateTlb
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DSB
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ISB
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mov r0,#0
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mcr p15,0,r0,c8,c7,0
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DSB
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ISB
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bx lr
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ArmSetTranslationTableBaseAddress
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DSB
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ISB
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mcr p15,0,r0,c2,c0,0
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DSB
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ISB
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bx lr
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ArmGetTranslationTableBaseAddress
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DSB
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ISB
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mrc p15,0,r0,c2,c0,0
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DSB
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ISB
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bx lr
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ArmSetDomainAccessControl
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DSB
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ISB
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mcr p15,0,r0,c3,c0,0
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DSB
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ISB
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bx lr
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CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
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DSB
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ISB
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stmfd sp!, {r4-r12, lr} ; save all the banked registers
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mov r3, sp ; copy the stack pointer into a non-banked register
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mrs r2, cpsr ; read the cpsr
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bic r2, r2, r0 ; clear mask in the cpsr
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and r1, r1, r0 ; clear bits outside the mask in the input
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orr r2, r2, r1 ; set field
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msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
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mov sp, r3 ; restore stack pointer
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ldmfd sp!, {r4-r12, lr} ; restore registers
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DSB
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ISB
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bx lr ; return (hopefully thumb-safe!)
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CPSRRead
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DSB
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ISB
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mrs r0, cpsr
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DSB
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ISB
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bx lr
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END
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