mirror of https://github.com/acidanthera/audk.git
216 lines
4.7 KiB
NASM
216 lines
4.7 KiB
NASM
//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
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//
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// All rights reserved. This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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EXPORT ArmInvalidateInstructionCache
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EXPORT ArmInvalidateDataCacheEntryByMVA
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EXPORT ArmCleanDataCacheEntryByMVA
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EXPORT ArmCleanInvalidateDataCacheEntryByMVA
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EXPORT ArmInvalidateDataCacheEntryBySetWay
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EXPORT ArmCleanDataCacheEntryBySetWay
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EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
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EXPORT ArmDrainWriteBuffer
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EXPORT ArmEnableMmu
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EXPORT ArmDisableMmu
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EXPORT ArmMmuEnabled
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EXPORT ArmEnableDataCache
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EXPORT ArmDisableDataCache
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EXPORT ArmEnableInstructionCache
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EXPORT ArmDisableInstructionCache
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EXPORT ArmEnableBranchPrediction
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EXPORT ArmDisableBranchPrediction
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DC_ON EQU ( 0x1:SHL:2 )
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IC_ON EQU ( 0x1:SHL:12 )
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XP_ON EQU ( 0x1:SHL:23 )
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AREA ArmCacheLib, CODE, READONLY
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PRESERVE8
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ArmInvalidateDataCacheEntryByMVA
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DSB
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ISB
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MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
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DSB
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ISB
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BX lr
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ArmCleanDataCacheEntryByMVA
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DSB
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ISB
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MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
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DSB
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ISB
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BX lr
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ArmCleanInvalidateDataCacheEntryByMVA
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DSB
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ISB
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MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
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DSB
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ISB
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BX lr
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ArmInvalidateDataCacheEntryBySetWay
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DSB
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ISB
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mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
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DSB
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ISB
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bx lr
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ArmCleanInvalidateDataCacheEntryBySetWay
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DSB
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ISB
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mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
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DSB
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ISB
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bx lr
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ArmCleanDataCacheEntryBySetWay
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DSB
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ISB
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mcr p15, 0, r0, c7, c10, 2 ; Clean this line
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DSB
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ISB
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bx lr
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ArmDrainWriteBuffer
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DSB
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ISB
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mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
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DSB
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ISB
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bx lr
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ArmInvalidateInstructionCache
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DSB
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ISB
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MOV R0,#0
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MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
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MOV R0,#0
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MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
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DSB
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ISB
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BX LR
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ArmEnableMmu
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DSB
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ISB
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mrc p15,0,R0,c1,c0,0
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orr R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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DSB
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ISB
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bx LR
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ArmMmuEnabled
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DSB
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ISB
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mrc p15,0,R0,c1,c0,0
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and R0,R0,#1
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DSB
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ISB
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bx LR
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ArmDisableMmu
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DSB
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ISB
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mov R0,#0
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mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
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mrc p15,0,R0,c1,c0,0
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0 ;Disable MMU
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
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mov R0,#0
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mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
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DSB
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ISB
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bx LR
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ArmEnableDataCache
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DSB
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ISB
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LDR R1,=DC_ON
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MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
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ORR R0,R0,R1 ;Set C bit
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MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
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DSB
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ISB
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BX LR
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ArmDisableDataCache
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DSB
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ISB
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LDR R1,=DC_ON
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MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
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BIC R0,R0,R1 ;Clear C bit
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MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
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DSB
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ISB
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BX LR
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ArmEnableInstructionCache
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DSB
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ISB
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LDR R1,=IC_ON
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MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
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ORR R0,R0,R1 ;Set I bit
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MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
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DSB
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ISB
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BX LR
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ArmDisableInstructionCache
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DSB
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ISB
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LDR R1,=IC_ON
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MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
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BIC R0,R0,R1 ;Clear I bit.
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MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
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DSB
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ISB
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BX LR
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ArmEnableBranchPrediction
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DSB
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ISB
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000800
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mcr p15, 0, r0, c1, c0, 0
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DSB
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ISB
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bx LR
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ArmDisableBranchPrediction
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DSB
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ISB
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00000800
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mcr p15, 0, r0, c1, c0, 0
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DSB
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ISB
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bx LR
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END
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