mirror of https://github.com/acidanthera/audk.git
193 lines
4.3 KiB
NASM
193 lines
4.3 KiB
NASM
//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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EXPORT Cp15IdCode
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EXPORT Cp15CacheInfo
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EXPORT ArmIsMPCore
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EXPORT ArmEnableAsynchronousAbort
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EXPORT ArmDisableAsynchronousAbort
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EXPORT ArmEnableIrq
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EXPORT ArmDisableIrq
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EXPORT ArmGetInterruptState
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EXPORT ArmEnableFiq
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EXPORT ArmDisableFiq
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EXPORT ArmEnableInterrupts
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EXPORT ArmDisableInterrupts
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EXPORT ArmGetFiqState
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EXPORT ArmInvalidateTlb
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EXPORT ArmSetTTBR0
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EXPORT ArmGetTTBR0BaseAddress
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EXPORT ArmSetDomainAccessControl
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EXPORT ArmUpdateTranslationTableEntry
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EXPORT CPSRMaskInsert
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EXPORT CPSRRead
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EXPORT ReadCCSIDR
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EXPORT ReadCLIDR
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AREA ArmLibSupport, CODE, READONLY
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//------------------------------------------------------------------------------
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Cp15IdCode
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mrc p15,0,R0,c0,c0,0
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bx LR
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Cp15CacheInfo
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mrc p15,0,R0,c0,c0,1
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bx LR
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ArmIsMPCore
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mrc p15,0,R0,c0,c0,5
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// Get Multiprocessing extension (bit31) & U bit (bit30)
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and R0, R0, #0xC0000000
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// if bit30 == 0 then the processor is part of a multiprocessor system)
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and R0, R0, #0x80000000
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bx LR
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ArmEnableAsynchronousAbort
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cpsie a
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isb
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bx LR
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ArmDisableAsynchronousAbort
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cpsid a
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isb
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bx LR
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ArmEnableIrq
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cpsie i
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isb
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bx LR
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ArmDisableIrq
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cpsid i
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isb
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bx LR
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ArmEnableFiq
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cpsie f
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isb
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bx LR
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ArmDisableFiq
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cpsid f
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isb
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bx LR
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ArmEnableInterrupts
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cpsie if
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isb
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bx LR
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ArmDisableInterrupts
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cpsid if
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isb
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bx LR
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ArmGetInterruptState
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mrs R0,CPSR
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tst R0,#0x80 ;Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ArmGetFiqState
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mrs R0,CPSR
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tst R0,#0x40 ;Check if FIQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ArmInvalidateTlb
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mov r0,#0
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mcr p15,0,r0,c8,c7,0
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mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
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dsb
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isb
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bx lr
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ArmSetTTBR0
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mcr p15,0,r0,c2,c0,0
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isb
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bx lr
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ArmGetTTBR0BaseAddress
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mrc p15,0,r0,c2,c0,0
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ldr r1, = 0xFFFFC000
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and r0, r0, r1
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isb
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bx lr
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ArmSetDomainAccessControl
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mcr p15,0,r0,c3,c0,0
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isb
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bx lr
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//
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//VOID
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//ArmUpdateTranslationTableEntry (
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// IN VOID *TranslationTableEntry // R0
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// IN VOID *MVA // R1
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// );
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ArmUpdateTranslationTableEntry
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mcr p15,0,R0,c7,c14,1 ; DCCIMVAC Clean data cache by MVA
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dsb
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mcr p15,0,R1,c8,c7,1 ; TLBIMVA TLB Invalidate MVA
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mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
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dsb
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isb
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bx lr
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CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
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stmfd sp!, {r4-r12, lr} ; save all the banked registers
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mov r3, sp ; copy the stack pointer into a non-banked register
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mrs r2, cpsr ; read the cpsr
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bic r2, r2, r0 ; clear mask in the cpsr
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and r1, r1, r0 ; clear bits outside the mask in the input
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orr r2, r2, r1 ; set field
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msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
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isb
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mov sp, r3 ; restore stack pointer
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ldmfd sp!, {r4-r12, lr} ; restore registers
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bx lr ; return (hopefully thumb-safe!)
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CPSRRead
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mrs r0, cpsr
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bx lr
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// UINT32
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// ReadCCSIDR (
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// IN UINT32 CSSELR
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// )
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ReadCCSIDR
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mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
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isb
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mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
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bx lr
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// UINT32
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// ReadCLIDR (
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// IN UINT32 CSSELR
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// )
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ReadCLIDR
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mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
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bx lr
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END
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