mirror of https://github.com/acidanthera/audk.git
156 lines
5.6 KiB
C
156 lines
5.6 KiB
C
/** @file
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Define the PPI to abstract the functions that enable IDE and SATA channels, and to retrieve
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the base I/O port address for each of the enabled IDE and SATA channels.
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PEI_ATA_CONTROLLER_PPI_H_
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#define _PEI_ATA_CONTROLLER_PPI_H_
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///
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/// Global ID for the PEI_ATA_CONTROLLER_PPI.
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///
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#define PEI_ATA_CONTROLLER_PPI_GUID \
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{ \
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0xa45e60d1, 0xc719, 0x44aa, {0xb0, 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d } \
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}
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///
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/// Forward declaration for the PEI_ATA_CONTROLLER_PPI.
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///
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typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
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///
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/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
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/// disable the IDE channels.
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/// This is designed for old generation chipset with PATA/SATA controllers.
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/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
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///
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#define PEI_ICH_IDE_NONE 0x00
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///
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/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
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/// enable the Primary IDE channel.
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/// This is designed for old generation chipset with PATA/SATA controllers.
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/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
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///
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#define PEI_ICH_IDE_PRIMARY 0x01
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///
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/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
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/// enable the Secondary IDE channel.
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/// This is designed for old generation chipset with PATA/SATA controllers.
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/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
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///
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#define PEI_ICH_IDE_SECONDARY 0x02
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///
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/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
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/// disable the SATA channel.
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/// This is designed for old generation chipset with PATA/SATA controllers.
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/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
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///
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#define PEI_ICH_SATA_NONE 0x04
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///
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/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
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/// enable the Primary SATA channel.
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/// This is designed for old generation chipset with PATA/SATA controllers.
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/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
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///
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#define PEI_ICH_SATA_PRIMARY 0x08
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///
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/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
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/// enable the Secondary SATA channel.
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/// This is designed for old generation chipset with PATA/SATA controllers.
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/// It may be ignored in PPI implementation for new generation chipset without PATA controller.
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///
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#define PEI_ICH_SATA_SECONDARY 0x010
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///
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/// Structure that contains the base addresses for the IDE registers
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///
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typedef struct {
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///
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/// Base I/O port address of the IDE controller's command block
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///
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UINT16 CommandBlockBaseAddr;
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///
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/// Base I/O port address of the IDE controller's control block
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///
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UINT16 ControlBlockBaseAddr;
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} IDE_REGS_BASE_ADDR;
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/**
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Sets IDE and SATA channels to an enabled or disabled state.
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This service enables or disables the IDE and SATA channels specified by ChannelMask.
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It may ignore ChannelMask setting to enable or disable IDE and SATA channels based on the platform policy.
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The number of the enabled channels will be returned by GET_IDE_REGS_BASE_ADDR() function.
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If the new state is set, then EFI_SUCCESS is returned. If the new state can
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not be set, then EFI_DEVICE_ERROR is returned.
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@param[in] PeiServices The pointer to the PEI Services Table.
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@param[in] This The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.
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@param[in] ChannelMask The bitmask that identifies the IDE and SATA channels to
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enable or disable. This parameter is optional.
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@retval EFI_SUCCESS The IDE or SATA channels were enabled or disabled successfully.
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@retval EFI_DEVICE_ERROR The IDE or SATA channels could not be enabled or disabled.
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**/
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typedef
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EFI_STATUS
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(EFIAPI *PEI_ENABLE_ATA)(
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IN EFI_PEI_SERVICES **PeiServices,
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IN PEI_ATA_CONTROLLER_PPI *This,
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IN UINT8 ChannelMask
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);
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/**
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Retrieves the I/O port base addresses for command and control registers of the
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enabled IDE/SATA channels.
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This service fills in the structure poionted to by IdeRegsBaseAddr with the I/O
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port base addresses for the command and control registers of the IDE and SATA
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channels that were previously enabled in EnableAtaChannel(). The number of
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enabled IDE and SATA channels is returned.
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@param[in] PeiServices The pointer to the PEI Services Table.
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@param[in] This The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.
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@param[out] IdeRegsBaseAddr The pointer to caller allocated space to return the
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I/O port base addresses of the IDE and SATA channels
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that were previosuly enabled with EnableAtaChannel().
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@return The number of enabled IDE and SATA channels in the platform.
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**/
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typedef
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UINT32
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(EFIAPI *GET_IDE_REGS_BASE_ADDR)(
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IN EFI_PEI_SERVICES **PeiServices,
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IN PEI_ATA_CONTROLLER_PPI *This,
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OUT IDE_REGS_BASE_ADDR *IdeRegsBaseAddr
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);
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///
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/// This PPI contains services to enable and disable IDE and SATA channels and
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/// retrieves the base I/O port addresses to the enabled IDE and SATA channels.
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///
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struct _PEI_ATA_CONTROLLER_PPI {
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PEI_ENABLE_ATA EnableAtaChannel;
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GET_IDE_REGS_BASE_ADDR GetIdeRegsBaseAddr;
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};
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extern EFI_GUID gPeiAtaControllerPpiGuid;
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#endif
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