mirror of https://github.com/acidanthera/audk.git
28f8d28faa
Unlike SGIs and PPIs, which are private to the CPU and are managed at the redistributor level (which is also a per-CPU construct), shared interrupts (SPIs) are shared between all CPUs, and therefore managed at the distributor level (just as on GICv2). Reported-by: Narinder Dhillon <ndhillonv2@gmail.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> |
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| .. | ||
| ArmCpuLib | ||
| ArmGic | ||
| ArmPciCpuIo2Dxe | ||
| CpuDxe | ||
| CpuPei | ||
| GenericWatchdogDxe | ||
| TimerDxe | ||