mirror of https://github.com/acidanthera/audk.git
157 lines
4.8 KiB
C
157 lines
4.8 KiB
C
/** @file
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This file declares PciCfg PPI used to access PCI configuration space in PEI
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Copyright (c) 2006 - 2007, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@par Revision Reference:
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This PPI is defined in PI
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Version 1.00.
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**/
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#ifndef __PEI_PCI_CFG2_H__
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#define __PEI_PCI_CFG2_H__
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#define EFI_PEI_PCI_CFG2_PPI_GUID \
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{ 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }
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typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI;
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#define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \
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(((bus) << 24) | \
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((dev) << 16) | \
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((func) << 8) | \
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((reg) < 256 ? (reg) : ((UINT64) (reg) << 32)));
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//
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// EFI_PEI_PCI_CFG_PPI_WIDTH
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//
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typedef enum {
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EfiPeiPciCfgWidthUint8 = 0,
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EfiPeiPciCfgWidthUint16 = 1,
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EfiPeiPciCfgWidthUint32 = 2,
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EfiPeiPciCfgWidthUint64 = 3,
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EfiPeiPciCfgWidthMaximum
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} EFI_PEI_PCI_CFG_PPI_WIDTH;
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//
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// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS
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//
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typedef struct {
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UINT8 Register;
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UINT8 Function;
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UINT8 Device;
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UINT8 Bus;
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UINT32 ExtendedRegister;
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} EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;
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/**
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Reads from or write to a given location in the PCI configuration space.
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@param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
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@param This Pointer to local data for the interface.
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@param Width The width of the access. Enumerated in bytes.
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See EFI_PEI_PCI_CFG_PPI_WIDTH above.
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@param Address The physical address of the access. The format of
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the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.
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@param Buffer A pointer to the buffer of data..
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@retval EFI_SUCCESS The function completed successfully.
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@retval EFI_DEVICE_ERROR There was a problem with the transaction.
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@retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this
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time.
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**/
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typedef
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EFI_STATUS
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(EFIAPI *EFI_PEI_PCI_CFG2_PPI_IO) (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN CONST EFI_PEI_PCI_CFG2_PPI *This,
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IN CONST EFI_PEI_PCI_CFG_PPI_WIDTH Width,
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IN CONST UINT64 Address,
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IN OUT VOID *Buffer
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);
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/**
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PCI read-modify-write operation.
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@param PeiServices An indirect pointer to the PEI Services Table
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published by the PEI Foundation.
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@param This Pointer to local data for the interface.
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@param Width The width of the access. Enumerated in bytes. Type
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EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().
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@param Address The physical address of the access.
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@param SetBits Points to value to bitwise-OR with the read configuration value.
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The size of the value is determined by Width.
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@param ClearBits Points to the value to negate and bitwise-AND with the read configuration value.
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The size of the value is determined by Width.
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@retval EFI_SUCCESS The function completed successfully.
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@retval EFI_DEVICE_ERROR There was a problem with the transaction.
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@retval EFI_DEVICE_NOT_READY The device is not capable of supporting
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the operation at this time.
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**/
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typedef
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EFI_STATUS
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(EFIAPI *EFI_PEI_PCI_CFG2_PPI_RW) (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN CONST EFI_PEI_PCI_CFG2_PPI *This,
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IN CONST EFI_PEI_PCI_CFG_PPI_WIDTH Width,
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IN CONST UINT64 Address,
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IN CONST VOID *SetBits,
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IN CONST VOID *ClearBits
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);
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/**
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@par Ppi Description:
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The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI
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controllers behind a PCI root bridge controller.
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@param Read PCI read services. See the Read() function description.
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@param Write PCI write services. See the Write() function description.
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@param Modify PCI read-modify-write services. See the Modify() function description.
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@param Segment The PCI bus segment which the specified functions will access.
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**/
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struct _EFI_PEI_PCI_CFG2_PPI {
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EFI_PEI_PCI_CFG2_PPI_IO Read;
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EFI_PEI_PCI_CFG2_PPI_IO Write;
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EFI_PEI_PCI_CFG2_PPI_RW Modify;
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UINT16 Segment;
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};
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extern EFI_GUID gEfiPciCfg2PpiGuid;
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#endif
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