mirror of https://github.com/acidanthera/audk.git
3fd8800954
implementation. Implement RISC-V CPU related functions in BaseCpuLib. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com> |
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| .. | ||
| AArch64 | ||
| Arm | ||
| Ebc | ||
| Ia32 | ||
| RiscV | ||
| X64 | ||
| BaseCpuLib.inf | ||
| BaseCpuLib.uni | ||