mirror of https://github.com/acidanthera/audk.git
148 lines
6.0 KiB
C
148 lines
6.0 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <ArmPlatform.h>
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// Number of Virtual Memory Map Descriptors without a Logic Tile
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 5
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// DDR attributes
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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/**
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Return the Virtual Memory Map of your platform
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This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
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@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
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Virtual Memory mapping. This array must be ended by a zero-filled
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entry
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**/
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VOID
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ArmPlatformGetVirtualMemoryMap (
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IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
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)
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{
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ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
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UINTN Index = 0;
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ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
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ASSERT(VirtualMemoryMap != NULL);
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VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
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if (VirtualMemoryTable == NULL) {
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return;
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}
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if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
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CacheAttributes = DDR_ATTRIBUTES_CACHED;
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} else {
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CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
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}
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// ReMap (Either NOR Flash or DRAM)
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VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;
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if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {
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// Map the NOR Flash as Secure Memory
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if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
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VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
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} else {
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VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_UNCACHED;
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}
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} else {
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// DRAM mapping
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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}
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// DDR
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// CPU peripherals. TRM. Manual says not all of them are implemented.
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE;
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// SMB CS0-CS1 - NOR Flash 1 & 2
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE;
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// SMB CS2 - SRAM
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// Peripheral CS2 and CS3
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
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VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE;
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//TODO:This should be enabled for final release. Right now, ARM VE RTSM crashes.
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// // If a Logic Tile is connected to The ARM Versatile Express Motherboard
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// if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {
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// VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;
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// VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE;
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// VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ;
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// VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE;
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//
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// ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));
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// } else {
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// ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
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// }
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// End of Table
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VirtualMemoryTable[++Index].PhysicalBase = 0;
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VirtualMemoryTable[Index].VirtualBase = 0;
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VirtualMemoryTable[Index].Length = 0;
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VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
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*VirtualMemoryMap = VirtualMemoryTable;
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}
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/**
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Return the EFI Memory Map provided by extension memory on your platform
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This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
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Descriptor HOBs used by DXE core.
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TODO: CompleteMe .... say this is the memory not covered by the System Memory PCDs
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@param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
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EFI Memory region. This array must be ended by a zero-filled entry
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**/
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EFI_STATUS
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ArmPlatformGetAdditionalSystemMemory (
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OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
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)
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{
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return EFI_UNSUPPORTED;
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}
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