mirror of https://github.com/acidanthera/audk.git
94 lines
3.1 KiB
ArmAsm
94 lines
3.1 KiB
ArmAsm
#========================================================================================
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# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http:#opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#=======================================================================================
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#include <AsmMacroIoLibV8.h>
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#include <Chipset/AArch64.h>
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#start of the code section
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.text
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.align 3
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GCC_ASM_EXPORT(SwitchToNSExceptionLevel1)
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GCC_ASM_EXPORT(enter_monitor_mode)
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GCC_ASM_EXPORT(return_from_exception)
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GCC_ASM_EXPORT(copy_cpsr_into_spsr)
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GCC_ASM_EXPORT(set_non_secure_mode)
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// Switch from EL3 to NS-EL1
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ASM_PFX(SwitchToNSExceptionLevel1):
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// Now setup our EL1. Controlled by EL2 config on Model
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mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
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orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
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// Send all interrupts to their respective Exception levels for EL2
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and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable virtual FIQ, IRQ, SError and Abort
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msr hcr_el2, x0 // Write back our settings
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msr cptr_el2, xzr // Disable copro traps to EL2
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msr sctlr_el2, xzr
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// Enable architected timer access
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mrs x0, cnthctl_el2
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orr x0, x0, #3 // Enable EL1 access to timers
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msr cnthctl_el2, x0
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mrs x0, cntkctl_el1
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orr x0, x0, #3 // EL0 access to counters
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msr cntkctl_el1, x0
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// Set ID regs
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mrs x0, midr_el1
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mrs x1, mpidr_el1
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msr vpidr_el2, x0
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msr vmpidr_el2, x1
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ret
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// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7
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// we don't need a mode switch, just setup the Arguments and jump.
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// x0: Monitor World EntryPoint
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// x1: MpId
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// x2: SecBootMode
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// x3: Secure Monitor mode stack
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ASM_PFX(enter_monitor_mode):
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mov x4, x0 // Swap EntryPoint and MpId registers
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mov x0, x1
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mov x1, x2
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mov x2, x3
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br x4
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// Put the address in correct ELR_ELx and do a eret.
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// We may need to do some config before we change to another Mode.
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ASM_PFX(return_from_exception):
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msr elr_el3, x0
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eret
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// For AArch64 we need to construct the spsr we want from individual bits and pieces.
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ASM_PFX(copy_cpsr_into_spsr):
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mrs x0, CurrentEl // Get the current exception level we are running at.
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mrs x1, SPSel // Which Stack are we using
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orr x0, x0, x1
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mrs x1, daif // Which interrupts are enabled
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orr x0, x0, x1
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msr spsr_el3, x0 // Write to spsr
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ret
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// Get this from platform file.
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ASM_PFX(set_non_secure_mode):
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msr spsr_el3, x0
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ret
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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