Olivier Martin 48ef4e4276 ArmPkg/CpuDxe/AArch64: Fixed SyncCacheConfig() when first entry is in 3-level ... If the first entry of the memory map is in the third level (case when the region at 0x0 is smaller than 4KB) then its descriptor type would be TT_TYPE_BLOCK_ENTRY_LEVEL3 (=0x3) which has the same value as TT_TYPE_TABLE_ENTRY (=0x3). The first condition in GetFirstPageAttribute() needed the table level to not mix these two descriptor types. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15526 6f19259b-4bc3-4df7-8a09-765794883524		2014-05-14 05:32:07 +00:00
..
ArmCpuLib	ArmPkg/ArmCpuLib: Added A57 Errata 806969	2014-03-26 19:35:17 +00:00
ArmGic	ARM Packages: Renamed PL390Gic driver into ArmGic driver	2013-10-29 06:36:34 +00:00
CpuDxe	ArmPkg/CpuDxe/AArch64: Fixed SyncCacheConfig() when first entry is in 3-level	2014-05-14 05:32:07 +00:00
CpuPei	ArmPlatformPkg/ArmVExpressPkg: Removed unused PCDs declaration from INF file	2013-11-28 21:37:10 +00:00
TimerDxe	ArmPkg: Added Aarch64 support	2013-07-18 18:07:46 +00:00