mirror of https://github.com/acidanthera/audk.git
144 lines
4.2 KiB
C
144 lines
4.2 KiB
C
/** @file
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* Main file supporting the transition to PEI Core in Normal World for Versatile Express
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/IoLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugAgentLib.h>
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#include <Library/PrintLib.h>
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#include <Library/ArmLib.h>
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#include <Library/SerialPortLib.h>
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#include <Chipset/ArmV7.h>
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#include "PrePeiCore.h"
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EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport};
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EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
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&gEfiTemporaryRamSupportPpiGuid,
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&mSecTemporaryRamSupportPpi
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}
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};
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VOID
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CEntryPoint (
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IN UINTN CoreId,
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
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)
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{
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//Clean Data cache
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ArmCleanInvalidateDataCache();
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//Invalidate instruction cache
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ArmInvalidateInstructionCache();
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// Enable Instruction & Data caches
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ArmEnableDataCache ();
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ArmEnableInstructionCache ();
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//
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// Note: Doesn't have to Enable CPU interface in non-secure world,
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// as Non-secure interface is already enabled in Secure world.
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//
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// Write VBAR - The Vector table must be 32-byte aligned
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ASSERT(((UINT32)PeiVectorTable & ((1 << 5)-1)) == 0);
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ArmWriteVBar((UINT32)PeiVectorTable);
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//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
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//If not primary Jump to Secondary Main
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if(0 == CoreId) {
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// Initialize the Debug Agent for Source Level Debugging
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InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
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SaveAndSetDebugTimerInterrupt (TRUE);
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// Goto primary Main.
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PrimaryMain (PeiCoreEntryPoint);
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} else {
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SecondaryMain (CoreId);
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}
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// PEI Core should always load and never return
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ASSERT (FALSE);
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}
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EFI_STATUS
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EFIAPI
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SecTemporaryRamSupport (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
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IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
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IN UINTN CopySize
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)
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{
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//
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// Migrate the whole temporary memory to permenent memory.
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//
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CopyMem (
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(VOID*)(UINTN)PermanentMemoryBase,
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(VOID*)(UINTN)TemporaryMemoryBase,
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CopySize
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);
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SecSwitchStack((UINTN)(PermanentMemoryBase - TemporaryMemoryBase));
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return EFI_SUCCESS;
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}
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VOID
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PeiCommonExceptionEntry (
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IN UINT32 Entry,
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IN UINT32 LR
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)
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{
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CHAR8 Buffer[100];
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UINTN CharCount;
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switch (Entry) {
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case 0:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);
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break;
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case 1:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);
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break;
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case 2:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);
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break;
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case 3:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);
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break;
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case 4:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);
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break;
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case 5:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);
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break;
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case 6:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);
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break;
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case 7:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);
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break;
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default:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);
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break;
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}
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SerialPortWrite ((UINT8 *) Buffer, CharCount);
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while(1);
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}
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