mirror of https://github.com/acidanthera/audk.git
134 lines
4.8 KiB
Plaintext
134 lines
4.8 KiB
Plaintext
/** @file
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PCI express expansion ports
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef PcieExpansionPrt_asi
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#define PcieExpansionPrt_asi
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Device (PEX0) // PCI express bus bridged from [Bus 0, Device 23, Function 0]
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{
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Name(_ADR,0x00170000) // Device (HI WORD)=23, Func (LO WORD)=0
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Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#
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OperationRegion (PES0,PCI_Config,0x40,0xA0)
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Field (PES0, AnyAcc, NoLock, Preserve)
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{
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Offset(0x1A), // SLSTS - Slot Status Register
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ABP0, 1, // Bit 0, Attention Button Pressed
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, 2,
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PDC0, 1, // Bit 3, Presence Detect Changed
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, 2,
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PDS0, 1, // Bit 6, Presence Detect State
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, 1,
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LSC0, 1, // Bit 8, Link Active State Changed
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offset (0x20),
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, 16,
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PMS0, 1, // Bit 16, PME Status
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offset (0x98),
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, 30,
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HPE0, 1, // Bit 30, Hot Plug SCI Enable
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PCE0, 1, // Bit 31, Power Management SCI Enable.
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, 30,
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HPS0, 1, // Bit 30, Hot Plug SCI Status
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PCS0, 1, // Bit 31, Power Management SCI Status.
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}
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Method(_PRT,0,NotSerialized) {
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If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
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{
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Return (
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Package()
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{
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// Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH
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Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKE, 0}, // PCI Slot 1
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Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKF, 0},
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Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKG, 0},
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Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKH, 0},
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}
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)
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}
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else // IOAPIC Routing
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{
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Return (
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Package()
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{
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// Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH
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Package() {0x0000ffff, 0, 0, 20}, // PCI Slot 1
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Package() {0x0000ffff, 1, 0, 21},
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Package() {0x0000ffff, 2, 0, 22},
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Package() {0x0000ffff, 3, 0, 23},
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}
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)
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}
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}
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}
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Device (PEX1) // PCI express bus bridged from [Bus 0, Device 23, Function 1]
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{
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Name(_ADR,0x00170001) // Device (HI WORD)=23, Func (LO WORD)=1
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Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#
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OperationRegion (PES1,PCI_Config,0x40,0xA0)
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Field (PES1, AnyAcc, NoLock, Preserve)
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{
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Offset(0x1A), // SLSTS - Slot Status Register
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ABP1, 1, // Bit 0, Attention Button Pressed
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, 2,
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PDC1, 1, // Bit 3, Presence Detect Changed
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, 2,
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PDS1, 1, // Bit 6, Presence Detect State
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, 1,
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LSC1, 1, // Bit 8, Link Active State Changed
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offset (0x20),
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, 16,
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PMS1, 1, // Bit 16, PME Status
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offset (0x98),
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, 30,
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HPE1, 1, // Bit 30, Hot Plug SCI Enable
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PCE1, 1, // Bit 31, Power Management SCI Enable.
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, 30,
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HPS1, 1, // Bit 30, Hot Plug SCI Status
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PCS1, 1, // Bit 31, Power Management SCI Status.
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}
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Method(_PRT,0,NotSerialized) {
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If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
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{
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Return (
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Package()
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{
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// Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE
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Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKF, 0},
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Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKG, 0},
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Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKH, 0},
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Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKE, 0},
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}
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)
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}
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else // IOAPIC Routing
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{
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Return (
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Package()
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{
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// Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE
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Package() {0x0000ffff, 0, 0, 21},
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Package() {0x0000ffff, 1, 0, 22},
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Package() {0x0000ffff, 2, 0, 23},
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Package() {0x0000ffff, 3, 0, 20},
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}
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)
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}
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}
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}
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#endif
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