mirror of https://github.com/acidanthera/audk.git
73 lines
1.7 KiB
C
73 lines
1.7 KiB
C
/** @file
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HTE handling routines for MRC use.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __HTE_H
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#define __HTE_H
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#define STATIC static
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#define VOID void
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#if !defined(__GNUC__) && (__STDC_VERSION__ < 199901L)
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typedef uint32_t UINT32;
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typedef uint16_t UINT16;
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typedef uint8_t UINT8;
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#endif
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typedef enum
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{
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MrcNoHaltSystemOnError,
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MrcHaltSystemOnError,
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MrcHaltHteEngineOnError,
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MrcNoHaltHteEngineOnError
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} HALT_TYPE;
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typedef enum
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{
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MrcMemInit, MrcMemTest
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} MEM_INIT_OR_TEST;
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#define READ_TRAIN 1
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#define WRITE_TRAIN 2
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#define HTE_MEMTEST_NUM 2
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#define HTE_LOOP_CNT 5 // EXP_LOOP_CNT field of HTE_CMD_CTL. This CANNOT be less than 4
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#define HTE_LFSR_VICTIM_SEED 0xF294BA21 // Random seed for victim.
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#define HTE_LFSR_AGRESSOR_SEED 0xEBA7492D // Random seed for aggressor.
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UINT32
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HteMemInit(
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MRC_PARAMS *CurrentMrcData,
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UINT8 MemInitFlag,
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UINT8 HaltHteEngineOnError);
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UINT16
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BasicWriteReadHTE(
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MRC_PARAMS *CurrentMrcData,
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UINT32 Address,
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UINT8 FirstRun,
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UINT8 Mode);
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UINT16
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WriteStressBitLanesHTE(
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MRC_PARAMS *CurrentMrcData,
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UINT32 Address,
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UINT8 FirstRun);
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VOID
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HteMemOp(
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UINT32 Address,
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UINT8 FirstRun,
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UINT8 IsWrite);
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#endif
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