Sunil V L c32c5911c4 BaseTools GenFw: Add support for R_RISCV_PCREL_LO12_S relocation ... Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3459 This patch adds support for R_RISCV_PCREL_LO12_S relocation type. The logic is same as existing R_RISCV_PCREL_LO12_I relocation except the difference between load vs store instruction formats. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Yuwei Chen <yuwei.chen@intel.com> Cc: Pete Batard <pete@akeo.ie> Cc: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Acked-by: Abner Chang <abner.chang@hpe.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>		2021-07-21 02:12:29 +00:00
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C	BaseTools GenFw: Add support for R_RISCV_PCREL_LO12_S relocation	2021-07-21 02:12:29 +00:00
Python	BaseTools: Enable the flag to treat dynamic pcd as dynamicEx	2021-07-12 07:40:07 +00:00