mirror of https://github.com/acidanthera/audk.git
76 lines
2.5 KiB
C
76 lines
2.5 KiB
C
/*++
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Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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Portions copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
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Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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--*/
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#ifndef __ARM_EB_UART_H__
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#define __ARM_EB_UART_H__
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#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds
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// EB constants
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#define EB_UART1_BASE 0x10009000
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// PL011 Registers
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#define UARTDR 0x000
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#define UARTRSR 0x004
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#define UARTECR 0x004
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#define UARTFR 0x018
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#define UARTILPR 0x020
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#define UARTIBRD 0x024
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#define UARTFBRD 0x028
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#define UARTLCR_H 0x02C
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#define UARTCR 0x030
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#define UARTIFLS 0x034
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#define UARTIMSC 0x038
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#define UARTRIS 0x03C
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#define UARTMIS 0x040
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#define UARTICR 0x044
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#define UARTDMACR 0x048
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// If the required baud rate is 115200 and UARTCLK = 24MHz then:
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// Baud Rate Divisor = (24×10^6)/(16×115200) = 13.020833
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// This means BRDI = 13 and BRDF = 0.020833
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// Therefore, fractional part, m = integer(0.020833×64) = integer(1.33331) = 1
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// Generated baud rate divider = 13+1/64 = 13.015625
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// Generated baud rate = (24×10^6)/(16×13.015625) = 115246.098
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// Error = (115246.098-115200)/115200 × 100 = 0.04%
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#define UART_115200_IDIV 13
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#define UART_115200_FDIV 1
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// add more baud rates here as needed
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// data status bits
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#define UART_DATA_ERROR_MASK 0x0F00
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// status reg bits
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#define UART_STATUS_ERROR_MASK 0x0F
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// flag reg bits
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#define UART_TX_EMPTY_FLAG_MASK 0x80
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#define UART_RX_FULL_FLAG_MASK 0x40
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#define UART_TX_FULL_FLAG_MASK 0x20
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#define UART_RX_EMPTY_FLAG_MASK 0x10
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#define UART_BUSY_FLAG_MASK 0x08
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// control reg bits
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#define UART_CTSEN_CONTROL_MASK 0x8000
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#define UART_RTSEN_CONTROL_MASK 0x4000
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#define UART_RTS_CONTROL_MASK 0x0800
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#define UART_DTR_CONTROL_MASK 0x0400
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#endif
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