mirror of https://github.com/acidanthera/audk.git
875 lines
28 KiB
C
875 lines
28 KiB
C
/** @file
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Generic driver using Hardware Sequencing registers.
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Copyright (c) 2017-2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "SpiCommon.h"
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SPI_INSTANCE *mSpiInstance = NULL;
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/**
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Get SPI Instance from library global data..
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@retval SpiInstance Return SPI instance
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**/
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SPI_INSTANCE *
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GetSpiInstance (
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VOID
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)
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{
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if (mSpiInstance == NULL) {
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mSpiInstance = AllocatePool (sizeof (SPI_INSTANCE));
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if (mSpiInstance == NULL) {
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return NULL;
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}
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ZeroMem (mSpiInstance, sizeof (SPI_INSTANCE));
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}
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return mSpiInstance;
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}
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/**
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Initialize an SPI library.
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@retval EFI_SUCCESS The protocol instance was properly initialized
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@retval EFI_NOT_FOUND The expected SPI info could not be found
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**/
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EFI_STATUS
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EFIAPI
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SpiConstructor (
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VOID
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)
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{
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UINT32 ScSpiBar0;
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UINT8 Comp0Density;
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SPI_INSTANCE *SpiInstance;
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EFI_HOB_GUID_TYPE *GuidHob;
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SPI_FLASH_INFO *SpiFlashInfo;
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//
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// Find SPI flash hob
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//
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GuidHob = GetFirstGuidHob (&gSpiFlashInfoGuid);
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if (GuidHob == NULL) {
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ASSERT (FALSE);
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return EFI_NOT_FOUND;
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}
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SpiFlashInfo = (SPI_FLASH_INFO *)GET_GUID_HOB_DATA (GuidHob);
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//
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// Initialize the SPI instance
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//
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SpiInstance = GetSpiInstance ();
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if (SpiInstance == NULL) {
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return EFI_NOT_FOUND;
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}
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DEBUG ((DEBUG_INFO, "SpiInstance = %08X\n", SpiInstance));
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SpiInstance->Signature = SC_SPI_PRIVATE_DATA_SIGNATURE;
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SpiInstance->Handle = NULL;
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//
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// Check the SPI address
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//
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if ((SpiFlashInfo->SpiAddress.AddressSpaceId != EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE) ||
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(SpiFlashInfo->SpiAddress.RegisterBitWidth != 32) ||
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(SpiFlashInfo->SpiAddress.RegisterBitOffset != 0) ||
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(SpiFlashInfo->SpiAddress.AccessSize != EFI_ACPI_3_0_DWORD))
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{
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DEBUG ((DEBUG_ERROR, "SPI FLASH HOB is not expected. need check the hob or enhance SPI flash driver.\n"));
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}
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SpiInstance->PchSpiBase = (UINT32)(UINTN)SpiFlashInfo->SpiAddress.Address;
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SpiInstance->Flags = SpiFlashInfo->Flags;
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DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase));
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ScSpiBar0 = AcquireSpiBar0 (SpiInstance->PchSpiBase);
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DEBUG ((DEBUG_INFO, "ScSpiBar0 at 0x%08X\n", ScSpiBar0));
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if (ScSpiBar0 == 0) {
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ASSERT (FALSE);
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}
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if ((MmioRead32 (ScSpiBar0 + R_SPI_HSFS) & B_SPI_HSFS_FDV) == 0) {
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DEBUG ((DEBUG_ERROR, "SPI Flash descriptor invalid, cannot use Hardware Sequencing registers!\n"));
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ASSERT (FALSE);
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}
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MmioOr32 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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SpiInstance->RegionPermission = MmioRead16 (ScSpiBar0 + R_SPI_FRAP);
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SpiInstance->SfdpVscc0Value = MmioRead32 (ScSpiBar0 + R_SPI_LVSCC);
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SpiInstance->SfdpVscc1Value = MmioRead32 (ScSpiBar0 + R_SPI_UVSCC);
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//
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// Select to Flash Map 0 Register to get the number of flash Component
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//
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MmioAndThenOr32 (
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ScSpiBar0 + R_SPI_FDOC,
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(UINT32)(~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
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(UINT32)(V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP0)
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);
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//
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// Copy Zero based Number Of Components
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//
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SpiInstance->NumberOfComponents = (UINT8)((MmioRead16 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FDBAR_NC) >> N_SPI_FDBAR_NC);
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MmioAndThenOr32 (
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ScSpiBar0 + R_SPI_FDOC,
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(UINT32)(~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
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(UINT32)(V_SPI_FDOC_FDSS_COMP | R_SPI_FCBA_FLCOMP)
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);
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//
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// Copy Component 0 Density
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//
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Comp0Density = (UINT8)MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FLCOMP_COMP1_MASK;
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SpiInstance->Component1StartAddr = (UINT32)(SIZE_512KB << Comp0Density);
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//
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// Select FLASH_MAP1 to get Flash SC Strap Base Address
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//
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MmioAndThenOr32 (
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(ScSpiBar0 + R_SPI_FDOC),
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(UINT32)(~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
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(UINT32)(V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP1)
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);
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SpiInstance->StrapBaseAddress = MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FDBAR_FPSBA;
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//
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// Align FPSBA with address bits for the SC Strap portion of flash descriptor
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//
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SpiInstance->StrapBaseAddress &= B_SPI_FDBAR_FPSBA;
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return EFI_SUCCESS;
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}
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/**
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Read data from the flash part.
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@param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
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@param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
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@param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
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@param[out] Buffer The Pointer to caller-allocated buffer containing the data received.
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It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
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@retval EFI_SUCCESS Command succeed.
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@retval EFI_INVALID_PARAMETER The parameters specified are not valid.
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@retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
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**/
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EFI_STATUS
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EFIAPI
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SpiFlashRead (
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IN FLASH_REGION_TYPE FlashRegionType,
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IN UINT32 Address,
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IN UINT32 ByteCount,
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OUT UINT8 *Buffer
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)
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{
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EFI_STATUS Status;
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Status = SendSpiCmd (FlashRegionType, FlashCycleRead, Address, ByteCount, Buffer);
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return Status;
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}
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/**
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Write data to the flash part.
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@param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
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@param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
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@param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
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@param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
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@retval EFI_SUCCESS Command succeed.
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@retval EFI_INVALID_PARAMETER The parameters specified are not valid.
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@retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
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**/
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EFI_STATUS
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EFIAPI
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SpiFlashWrite (
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IN FLASH_REGION_TYPE FlashRegionType,
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IN UINT32 Address,
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IN UINT32 ByteCount,
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IN UINT8 *Buffer
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)
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{
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EFI_STATUS Status;
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Status = SendSpiCmd (FlashRegionType, FlashCycleWrite, Address, ByteCount, Buffer);
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return Status;
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}
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/**
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Erase some area on the flash part.
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@param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
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@param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
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@param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
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@retval EFI_SUCCESS Command succeed.
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@retval EFI_INVALID_PARAMETER The parameters specified are not valid.
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@retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
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**/
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EFI_STATUS
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EFIAPI
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SpiFlashErase (
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IN FLASH_REGION_TYPE FlashRegionType,
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IN UINT32 Address,
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IN UINT32 ByteCount
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)
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{
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EFI_STATUS Status;
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Status = SendSpiCmd (FlashRegionType, FlashCycleErase, Address, ByteCount, NULL);
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return Status;
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}
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/**
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Read SFDP data from the flash part.
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@param[in] ComponentNumber The Component Number for chip select
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@param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle, the max number is 64
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@param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
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It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
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@retval EFI_SUCCESS Command succeed.
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@retval EFI_INVALID_PARAMETER The parameters specified are not valid.
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@retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
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**/
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EFI_STATUS
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EFIAPI
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SpiFlashReadSfdp (
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IN UINT8 ComponentNumber,
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IN UINT32 ByteCount,
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OUT UINT8 *SfdpData
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)
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{
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EFI_STATUS Status;
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UINT32 Address;
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SPI_INSTANCE *SpiInstance;
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SpiInstance = GetSpiInstance ();
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if (SpiInstance == NULL) {
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return EFI_DEVICE_ERROR;
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}
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if ((ByteCount > 64) || (ComponentNumber > SpiInstance->NumberOfComponents)) {
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ASSERT (FALSE);
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return EFI_INVALID_PARAMETER;
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}
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Address = 0;
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if (ComponentNumber == FlashComponent1) {
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Address = SpiInstance->Component1StartAddr;
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}
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Status = SendSpiCmd (0, FlashCycleReadSfdp, Address, ByteCount, SfdpData);
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return Status;
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}
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/**
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Read Jedec Id from the flash part.
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@param[in] ComponentNumber The Component Number for chip select
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@param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
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@param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
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It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
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@retval EFI_SUCCESS Command succeed.
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@retval EFI_INVALID_PARAMETER The parameters specified are not valid.
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@retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
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**/
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EFI_STATUS
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EFIAPI
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SpiFlashReadJedecId (
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IN UINT8 ComponentNumber,
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IN UINT32 ByteCount,
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OUT UINT8 *JedecId
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)
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{
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EFI_STATUS Status;
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UINT32 Address;
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SPI_INSTANCE *SpiInstance;
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SpiInstance = GetSpiInstance ();
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if (SpiInstance == NULL) {
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return EFI_DEVICE_ERROR;
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}
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if (ComponentNumber > SpiInstance->NumberOfComponents) {
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ASSERT (FALSE);
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return EFI_INVALID_PARAMETER;
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}
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Address = 0;
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if (ComponentNumber == FlashComponent1) {
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Address = SpiInstance->Component1StartAddr;
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}
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Status = SendSpiCmd (0, FlashCycleReadJedecId, Address, ByteCount, JedecId);
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return Status;
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}
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/**
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Write the status register in the flash part.
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@param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
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@param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
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@retval EFI_SUCCESS Command succeed.
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@retval EFI_INVALID_PARAMETER The parameters specified are not valid.
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@retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
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**/
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EFI_STATUS
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EFIAPI
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SpiFlashWriteStatus (
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IN UINT32 ByteCount,
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IN UINT8 *StatusValue
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)
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{
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EFI_STATUS Status;
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Status = SendSpiCmd (0, FlashCycleWriteStatus, 0, ByteCount, StatusValue);
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return Status;
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}
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/**
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Read status register in the flash part.
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@param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
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@param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
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@retval EFI_SUCCESS Command succeed.
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@retval EFI_INVALID_PARAMETER The parameters specified are not valid.
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@retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
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**/
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EFI_STATUS
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EFIAPI
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SpiFlashReadStatus (
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IN UINT32 ByteCount,
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OUT UINT8 *StatusValue
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)
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{
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EFI_STATUS Status;
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Status = SendSpiCmd (0, FlashCycleReadStatus, 0, ByteCount, StatusValue);
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return Status;
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}
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/**
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Read SC Soft Strap Values
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@param[in] SoftStrapAddr SC Soft Strap address offset from FPSBA.
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@param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
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@param[out] SoftStrapValue The Pointer to caller-allocated buffer containing SC Soft Strap Value.
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It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
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@retval EFI_SUCCESS Command succeed.
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@retval EFI_INVALID_PARAMETER The parameters specified are not valid.
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@retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
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**/
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EFI_STATUS
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EFIAPI
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SpiReadPchSoftStrap (
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IN UINT32 SoftStrapAddr,
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IN UINT32 ByteCount,
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OUT UINT8 *SoftStrapValue
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)
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{
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UINT32 StrapFlashAddr;
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EFI_STATUS Status;
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SPI_INSTANCE *SpiInstance;
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SpiInstance = GetSpiInstance ();
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if (SpiInstance == NULL) {
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return EFI_DEVICE_ERROR;
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}
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ASSERT (SpiInstance->StrapBaseAddress != 0);
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//
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// SC Strap Flash Address = FPSBA + RamAddr
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//
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StrapFlashAddr = SpiInstance->StrapBaseAddress + SoftStrapAddr;
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Status = SendSpiCmd (FlashRegionDescriptor, FlashCycleRead, StrapFlashAddr, ByteCount, SoftStrapValue);
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return Status;
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}
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/**
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This function sends the programmed SPI command to the slave device.
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@param[in] FlashRegionType The SPI Region type for flash cycle which is listed in the Descriptor
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@param[in] FlashCycleType The Flash SPI cycle type list in HSFC (Hardware Sequencing Flash Control Register) register
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@param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
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@param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
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@param[in,out] Buffer Pointer to caller-allocated buffer containing the data received or sent during the SPI cycle.
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@retval EFI_SUCCESS SPI command completes successfully.
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@retval EFI_DEVICE_ERROR Device error, the command aborts abnormally.
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@retval EFI_ACCESS_DENIED Some unrecognized command encountered in hardware sequencing mode
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@retval EFI_INVALID_PARAMETER The parameters specified are not valid.
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**/
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EFI_STATUS
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SendSpiCmd (
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IN FLASH_REGION_TYPE FlashRegionType,
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IN FLASH_CYCLE_TYPE FlashCycleType,
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IN UINT32 Address,
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IN UINT32 ByteCount,
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IN OUT UINT8 *Buffer
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)
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{
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EFI_STATUS Status;
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UINT32 Index;
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UINTN SpiBaseAddress;
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UINT32 ScSpiBar0;
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UINT32 LimitAddress;
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UINT32 HardwareSpiAddr;
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UINT16 PermissionBit;
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UINT32 SpiDataCount;
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UINT32 FlashCycle;
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UINT8 BiosCtlSave;
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SPI_INSTANCE *SpiInstance;
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UINT32 Data32;
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SpiInstance = GetSpiInstance ();
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if (SpiInstance == NULL) {
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return EFI_DEVICE_ERROR;
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}
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Status = EFI_SUCCESS;
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SpiBaseAddress = SpiInstance->PchSpiBase;
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ScSpiBar0 = AcquireSpiBar0 (SpiBaseAddress);
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BiosCtlSave = 0;
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SpiInstance->RegionPermission = MmioRead16 (ScSpiBar0 + R_SPI_FRAP);
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//
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// If it's write cycle, disable Prefetching, Caching and disable BIOS Write Protect
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//
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if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleErase)) {
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Status = DisableBiosWriteProtect (SpiBaseAddress, mSpiInstance->Flags & FLAGS_SPI_DISABLE_SMM_WRITE_PROTECT);
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if (EFI_ERROR (Status)) {
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goto SendSpiCmdEnd;
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}
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BiosCtlSave = SaveAndDisableSpiPrefetchCache (SpiBaseAddress);
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}
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//
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// Make sure it's safe to program the command.
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//
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if (!WaitForSpiCycleComplete (ScSpiBar0, FALSE)) {
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Status = EFI_DEVICE_ERROR;
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goto SendSpiCmdEnd;
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}
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HardwareSpiAddr = Address;
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if ((FlashCycleType == FlashCycleRead) ||
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(FlashCycleType == FlashCycleWrite) ||
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(FlashCycleType == FlashCycleErase))
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{
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switch (FlashRegionType) {
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case FlashRegionDescriptor:
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if (FlashCycleType == FlashCycleRead) {
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PermissionBit = B_SPI_FRAP_BRRA_FLASHD;
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} else {
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PermissionBit = B_SPI_FRAP_BRWA_FLASHD;
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}
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Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD);
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HardwareSpiAddr += (Data32 & B_SPI_FREG0_BASE_MASK) << N_SPI_FREG0_BASE;
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LimitAddress = (Data32 & B_SPI_FREG0_LIMIT_MASK) >> N_SPI_FREG0_LIMIT;
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break;
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case FlashRegionBios:
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if (FlashCycleType == FlashCycleRead) {
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PermissionBit = B_SPI_FRAP_BRRA_BIOS;
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} else {
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PermissionBit = B_SPI_FRAP_BRWA_BIOS;
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}
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Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG1_BIOS);
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HardwareSpiAddr += (Data32 & B_SPI_FREG1_BASE_MASK) << N_SPI_FREG1_BASE;
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LimitAddress = (Data32 & B_SPI_FREG1_LIMIT_MASK) >> N_SPI_FREG1_LIMIT;
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break;
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case FlashRegionMe:
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if (FlashCycleType == FlashCycleRead) {
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PermissionBit = B_SPI_FRAP_BRRA_SEC;
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} else {
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|
PermissionBit = B_SPI_FRAP_BRWA_SEC;
|
|
}
|
|
|
|
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG2_SEC);
|
|
HardwareSpiAddr += (Data32 & B_SPI_FREG2_BASE_MASK) << N_SPI_FREG2_BASE;
|
|
LimitAddress = (Data32 & B_SPI_FREG2_LIMIT_MASK) >> N_SPI_FREG2_LIMIT;
|
|
break;
|
|
|
|
case FlashRegionGbE:
|
|
if (FlashCycleType == FlashCycleRead) {
|
|
PermissionBit = B_SPI_FRAP_BRRA_GBE;
|
|
} else {
|
|
PermissionBit = B_SPI_FRAP_BRWA_GBE;
|
|
}
|
|
|
|
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG3_GBE);
|
|
HardwareSpiAddr += (Data32 & B_SPI_FREG3_BASE_MASK) << N_SPI_FREG3_BASE;
|
|
LimitAddress = (Data32 & B_SPI_FREG3_LIMIT_MASK) >> N_SPI_FREG3_LIMIT;
|
|
break;
|
|
|
|
case FlashRegionPlatformData:
|
|
if (FlashCycleType == FlashCycleRead) {
|
|
PermissionBit = B_SPI_FRAP_BRRA_PLATFORM;
|
|
} else {
|
|
PermissionBit = B_SPI_FRAP_BRWA_PLATFORM;
|
|
}
|
|
|
|
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG4_PLATFORM_DATA);
|
|
HardwareSpiAddr += (Data32 & B_SPI_FREG4_BASE_MASK) << N_SPI_FREG4_BASE;
|
|
LimitAddress = (Data32 & B_SPI_FREG4_LIMIT_MASK) >> N_SPI_FREG4_LIMIT;
|
|
break;
|
|
|
|
case FlashRegionAll:
|
|
//
|
|
// FlashRegionAll indicates address is relative to flash device
|
|
// No error checking for this case
|
|
//
|
|
LimitAddress = 0;
|
|
PermissionBit = 0;
|
|
break;
|
|
|
|
default:
|
|
Status = EFI_UNSUPPORTED;
|
|
goto SendSpiCmdEnd;
|
|
}
|
|
|
|
if ((LimitAddress != 0) && (Address > LimitAddress)) {
|
|
Status = EFI_INVALID_PARAMETER;
|
|
goto SendSpiCmdEnd;
|
|
}
|
|
|
|
//
|
|
// If the operation is read, but the region attribute is not read allowed, return error.
|
|
// If the operation is write, but the region attribute is not write allowed, return error.
|
|
//
|
|
if ((PermissionBit != 0) && ((SpiInstance->RegionPermission & PermissionBit) == 0)) {
|
|
Status = EFI_ACCESS_DENIED;
|
|
goto SendSpiCmdEnd;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Check for SC SPI hardware sequencing required commands
|
|
//
|
|
FlashCycle = 0;
|
|
switch (FlashCycleType) {
|
|
case FlashCycleRead:
|
|
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_READ << N_SPI_HSFS_CYCLE);
|
|
break;
|
|
|
|
case FlashCycleWrite:
|
|
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_WRITE << N_SPI_HSFS_CYCLE);
|
|
break;
|
|
|
|
case FlashCycleErase:
|
|
if (((ByteCount % SIZE_4KB) != 0) || ((HardwareSpiAddr % SIZE_4KB) != 0)) {
|
|
DEBUG ((DEBUG_ERROR, "Erase and erase size must be 4KB aligned. \n"));
|
|
ASSERT (FALSE);
|
|
Status = EFI_INVALID_PARAMETER;
|
|
goto SendSpiCmdEnd;
|
|
}
|
|
|
|
break;
|
|
|
|
case FlashCycleReadSfdp:
|
|
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_READ_SFDP << N_SPI_HSFS_CYCLE);
|
|
break;
|
|
|
|
case FlashCycleReadJedecId:
|
|
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_READ_JEDEC_ID << N_SPI_HSFS_CYCLE);
|
|
break;
|
|
|
|
case FlashCycleWriteStatus:
|
|
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_WRITE_STATUS << N_SPI_HSFS_CYCLE);
|
|
break;
|
|
|
|
case FlashCycleReadStatus:
|
|
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_READ_STATUS << N_SPI_HSFS_CYCLE);
|
|
break;
|
|
|
|
default:
|
|
//
|
|
// Unrecognized Operation
|
|
//
|
|
ASSERT (FALSE);
|
|
Status = EFI_INVALID_PARAMETER;
|
|
goto SendSpiCmdEnd;
|
|
break;
|
|
}
|
|
|
|
do {
|
|
SpiDataCount = ByteCount;
|
|
if ((FlashCycleType == FlashCycleRead) || (FlashCycleType == FlashCycleWrite)) {
|
|
//
|
|
// Trim at 256 byte boundary per operation,
|
|
// - SC SPI controller requires trimming at 4KB boundary
|
|
// - Some SPI chips require trimming at 256 byte boundary for write operation
|
|
// - Trimming has limited performance impact as we can read / write at most 64 byte
|
|
// per operation
|
|
//
|
|
if (HardwareSpiAddr + ByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 - 1))) {
|
|
SpiDataCount = (((UINT32)(HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32)(HardwareSpiAddr);
|
|
}
|
|
|
|
//
|
|
// Calculate the number of bytes to shift in/out during the SPI data cycle.
|
|
// Valid settings for the number of bytes during each data portion of the
|
|
// SC SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48, 56, 64
|
|
//
|
|
if (SpiDataCount >= 64) {
|
|
SpiDataCount = 64;
|
|
} else if ((SpiDataCount &~0x07) != 0) {
|
|
SpiDataCount = SpiDataCount &~0x07;
|
|
}
|
|
}
|
|
|
|
if (FlashCycleType == FlashCycleErase) {
|
|
if (((ByteCount / SIZE_64KB) != 0) &&
|
|
((ByteCount % SIZE_64KB) == 0) &&
|
|
((HardwareSpiAddr % SIZE_64KB) == 0))
|
|
{
|
|
if (HardwareSpiAddr < SpiInstance->Component1StartAddr) {
|
|
//
|
|
// Check whether Component0 support 64k Erase
|
|
//
|
|
if ((SpiInstance->SfdpVscc0Value & B_SPI_LVSCC_EO_64K) != 0) {
|
|
SpiDataCount = SIZE_64KB;
|
|
} else {
|
|
SpiDataCount = SIZE_4KB;
|
|
}
|
|
} else {
|
|
//
|
|
// Check whether Component1 support 64k Erase
|
|
//
|
|
if ((SpiInstance->SfdpVscc1Value & B_SPI_LVSCC_EO_64K) != 0) {
|
|
SpiDataCount = SIZE_64KB;
|
|
} else {
|
|
SpiDataCount = SIZE_4KB;
|
|
}
|
|
}
|
|
} else {
|
|
SpiDataCount = SIZE_4KB;
|
|
}
|
|
|
|
if (SpiDataCount == SIZE_4KB) {
|
|
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_4K_ERASE << N_SPI_HSFS_CYCLE);
|
|
} else {
|
|
FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_64K_ERASE << N_SPI_HSFS_CYCLE);
|
|
}
|
|
}
|
|
|
|
//
|
|
// If it's write cycle, load data into the SPI data buffer.
|
|
//
|
|
if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleWriteStatus)) {
|
|
if ((SpiDataCount & 0x07) != 0) {
|
|
//
|
|
// Use Byte write if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
|
|
//
|
|
for (Index = 0; Index < SpiDataCount; Index++) {
|
|
MmioWrite8 (ScSpiBar0 + R_SPI_FDATA00 + Index, Buffer[Index]);
|
|
}
|
|
} else {
|
|
//
|
|
// Use Dword write if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
|
|
//
|
|
for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
|
|
MmioWrite32 (ScSpiBar0 + R_SPI_FDATA00 + Index, *(UINT32 *)(Buffer + Index));
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// Set the Flash Address
|
|
//
|
|
MmioWrite32 (ScSpiBar0 + R_SPI_FADDR, (UINT32)(HardwareSpiAddr & B_SPI_FADDR_MASK));
|
|
|
|
//
|
|
// Set Data count, Flash cycle, and Set Go bit to start a cycle
|
|
//
|
|
MmioAndThenOr32 (
|
|
ScSpiBar0 + R_SPI_HSFS,
|
|
(UINT32)(~(B_SPI_HSFS_FDBC_MASK | B_SPI_HSFS_CYCLE_MASK)),
|
|
(UINT32)(((SpiDataCount - 1) << N_SPI_HSFS_FDBC) | FlashCycle | B_SPI_HSFS_CYCLE_FGO)
|
|
);
|
|
|
|
//
|
|
// Wait for command execution complete.
|
|
//
|
|
if (!WaitForSpiCycleComplete (ScSpiBar0, TRUE)) {
|
|
Status = EFI_DEVICE_ERROR;
|
|
goto SendSpiCmdEnd;
|
|
}
|
|
|
|
//
|
|
// If it's read cycle, load data into the caller's buffer.
|
|
//
|
|
if ((FlashCycleType == FlashCycleRead) ||
|
|
(FlashCycleType == FlashCycleReadSfdp) ||
|
|
(FlashCycleType == FlashCycleReadJedecId) ||
|
|
(FlashCycleType == FlashCycleReadStatus))
|
|
{
|
|
if ((SpiDataCount & 0x07) != 0) {
|
|
//
|
|
// Use Byte read if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
|
|
//
|
|
for (Index = 0; Index < SpiDataCount; Index++) {
|
|
Buffer[Index] = MmioRead8 (ScSpiBar0 + R_SPI_FDATA00 + Index);
|
|
}
|
|
} else {
|
|
//
|
|
// Use Dword read if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
|
|
//
|
|
for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
|
|
*(UINT32 *)(Buffer + Index) = MmioRead32 (ScSpiBar0 + R_SPI_FDATA00 + Index);
|
|
}
|
|
}
|
|
}
|
|
|
|
HardwareSpiAddr += SpiDataCount;
|
|
Buffer += SpiDataCount;
|
|
ByteCount -= SpiDataCount;
|
|
} while (ByteCount > 0);
|
|
|
|
SendSpiCmdEnd:
|
|
///
|
|
/// Restore the settings for SPI Prefetching and Caching and enable BIOS Write Protect
|
|
///
|
|
if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleErase)) {
|
|
EnableBiosWriteProtect (SpiBaseAddress, mSpiInstance->Flags & FLAGS_SPI_DISABLE_SMM_WRITE_PROTECT);
|
|
SetSpiBiosControlRegister (SpiBaseAddress, BiosCtlSave);
|
|
}
|
|
|
|
ReleaseSpiBar0 (SpiBaseAddress);
|
|
|
|
return Status;
|
|
}
|
|
|
|
/**
|
|
Wait execution cycle to complete on the SPI interface.
|
|
|
|
@param[in] ScSpiBar0 Spi MMIO base address
|
|
@param[in] ErrorCheck TRUE if the SpiCycle needs to do the error check
|
|
|
|
@retval TRUE SPI cycle completed on the interface.
|
|
@retval FALSE Time out while waiting the SPI cycle to complete.
|
|
It's not safe to program the next command on the SPI interface.
|
|
**/
|
|
BOOLEAN
|
|
WaitForSpiCycleComplete (
|
|
IN UINT32 ScSpiBar0,
|
|
IN BOOLEAN ErrorCheck
|
|
)
|
|
{
|
|
UINT64 WaitTicks;
|
|
UINT64 WaitCount;
|
|
UINT32 Data32;
|
|
|
|
//
|
|
// Convert the wait period allowed into to tick count
|
|
//
|
|
WaitCount = WAIT_TIME / WAIT_PERIOD;
|
|
//
|
|
// Wait for the SPI cycle to complete.
|
|
//
|
|
for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {
|
|
Data32 = MmioRead32 (ScSpiBar0 + R_SPI_HSFS);
|
|
if ((Data32 & B_SPI_HSFS_SCIP) == 0) {
|
|
MmioWrite32 (ScSpiBar0 + R_SPI_HSFS, B_SPI_HSFS_FCERR | B_SPI_HSFS_FDONE);
|
|
if (((Data32 & B_SPI_HSFS_FCERR) != 0) && ErrorCheck) {
|
|
return FALSE;
|
|
} else {
|
|
return TRUE;
|
|
}
|
|
}
|
|
|
|
MicroSecondDelay (WAIT_PERIOD);
|
|
}
|
|
|
|
return FALSE;
|
|
}
|
|
|
|
/**
|
|
Get the SPI region base and size, based on the enum type
|
|
|
|
@param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
|
|
@param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
|
|
@param[out] RegionSize The size for the Region 'n'
|
|
|
|
@retval EFI_SUCCESS Read success
|
|
@retval EFI_INVALID_PARAMETER Invalid region type given
|
|
@retval EFI_DEVICE_ERROR The region is not used
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
SpiGetRegionAddress (
|
|
IN FLASH_REGION_TYPE FlashRegionType,
|
|
OUT UINT32 *BaseAddress OPTIONAL,
|
|
OUT UINT32 *RegionSize OPTIONAL
|
|
)
|
|
{
|
|
UINT32 ScSpiBar0;
|
|
UINT32 ReadValue;
|
|
UINT32 Base;
|
|
SPI_INSTANCE *SpiInstance;
|
|
|
|
if (FlashRegionType >= FlashRegionMax) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
SpiInstance = GetSpiInstance ();
|
|
if (SpiInstance == NULL) {
|
|
return EFI_DEVICE_ERROR;
|
|
}
|
|
|
|
if (FlashRegionType == FlashRegionAll) {
|
|
if (BaseAddress != NULL) {
|
|
*BaseAddress = 0;
|
|
}
|
|
|
|
if (RegionSize != NULL) {
|
|
*RegionSize = SpiInstance->Component1StartAddr;
|
|
}
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
ScSpiBar0 = AcquireSpiBar0 (SpiInstance->PchSpiBase);
|
|
ReadValue = MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD + S_SPI_FREGX * (UINT32)FlashRegionType);
|
|
ReleaseSpiBar0 (SpiInstance->PchSpiBase);
|
|
|
|
//
|
|
// If the region is not used, the Region Base is 7FFFh and Region Limit is 0000h
|
|
//
|
|
if (ReadValue == B_SPI_FREGX_BASE_MASK) {
|
|
return EFI_DEVICE_ERROR;
|
|
}
|
|
|
|
Base = (ReadValue & B_SPI_FREG1_BASE_MASK) << N_SPI_FREG1_BASE;
|
|
if (BaseAddress != NULL) {
|
|
*BaseAddress = Base;
|
|
}
|
|
|
|
if (RegionSize != NULL) {
|
|
*RegionSize = ((((ReadValue & B_SPI_FREGX_LIMIT_MASK) >> N_SPI_FREGX_LIMIT) + 1) <<
|
|
N_SPI_FREGX_LIMIT_REPR) - Base;
|
|
}
|
|
|
|
return EFI_SUCCESS;
|
|
}
|