mirror of https://github.com/acidanthera/audk.git
135 lines
4.5 KiB
C
135 lines
4.5 KiB
C
/** @file
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AMD Sev Dxe driver. This driver is dispatched early in DXE, due to being list
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in APRIORI. It clears C-bit from MMIO and NonExistent Memory space when SEV
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is enabled.
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Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <IndustryStandard/Q35MchIch9.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/MemEncryptSevLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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EFI_STATUS
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EFIAPI
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AmdSevDxeEntryPoint (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_GCD_MEMORY_SPACE_DESCRIPTOR *AllDescMap;
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UINTN NumEntries;
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UINTN Index;
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//
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// Do nothing when SEV is not enabled
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//
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if (!MemEncryptSevIsEnabled ()) {
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return EFI_UNSUPPORTED;
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}
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//
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// Iterate through the GCD map and clear the C-bit from MMIO and NonExistent
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// memory space. The NonExistent memory space will be used for mapping the
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// MMIO space added later (eg PciRootBridge). By clearing both known MMIO and
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// NonExistent memory space can gurantee that current and furture MMIO adds
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// will have C-bit cleared.
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//
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Status = gDS->GetMemorySpaceMap (&NumEntries, &AllDescMap);
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if (!EFI_ERROR (Status)) {
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for (Index = 0; Index < NumEntries; Index++) {
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CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Desc;
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Desc = &AllDescMap[Index];
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if (Desc->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo ||
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Desc->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
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Status = MemEncryptSevClearMmioPageEncMask (
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0,
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Desc->BaseAddress,
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EFI_SIZE_TO_PAGES (Desc->Length)
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);
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ASSERT_EFI_ERROR (Status);
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}
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}
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FreePool (AllDescMap);
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}
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//
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// If PCI Express is enabled, the MMCONFIG area has been reserved, rather
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// than marked as MMIO, and so the C-bit won't be cleared by the above walk
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// through the GCD map. Check for the MMCONFIG area and clear the C-bit for
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// the range.
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//
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if (PcdGet16 (PcdOvmfHostBridgePciDevId) == INTEL_Q35_MCH_DEVICE_ID) {
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Status = MemEncryptSevClearMmioPageEncMask (
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0,
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FixedPcdGet64 (PcdPciExpressBaseAddress),
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EFI_SIZE_TO_PAGES (SIZE_256MB)
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);
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ASSERT_EFI_ERROR (Status);
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}
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//
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// When SMM is enabled, clear the C-bit from SMM Saved State Area
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//
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// NOTES: The SavedStateArea address cleared here is before SMBASE
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// relocation. Currently, we do not clear the SavedStateArea address after
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// SMBASE is relocated due to the following reasons:
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//
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// 1) Guest BIOS never access the relocated SavedStateArea.
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//
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// 2) The C-bit works on page-aligned address, but the SavedStateArea
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// address is not a page-aligned. Theoretically, we could roundup the address
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// and clear the C-bit of aligned address but looking carefully we found
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// that some portion of the page contains code -- which will causes a bigger
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// issues for SEV guest. When SEV is enabled, all the code must be encrypted
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// otherwise hardware will cause trap.
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//
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// We restore the C-bit for this SMM Saved State Area after SMBASE relocation
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// is completed (See OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c).
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//
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if (FeaturePcdGet (PcdSmmSmramRequire)) {
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UINTN MapPagesBase;
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UINTN MapPagesCount;
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Status = MemEncryptSevLocateInitialSmramSaveStateMapPages (
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&MapPagesBase,
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&MapPagesCount
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Although these pages were set aside (i.e., allocated) by PlatformPei, we
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// could be after a warm reboot from the OS. Don't leak any stale OS data
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// to the hypervisor.
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//
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ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount));
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Status = MemEncryptSevClearPageEncMask (
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0, // Cr3BaseAddress -- use current CR3
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MapPagesBase, // BaseAddress
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MapPagesCount // NumPages
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "%a: MemEncryptSevClearPageEncMask(): %r\n",
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__FUNCTION__, Status));
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ASSERT (FALSE);
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CpuDeadLoop ();
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}
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}
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return EFI_SUCCESS;
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}
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