mirror of https://github.com/acidanthera/audk.git
152 lines
4.1 KiB
C
152 lines
4.1 KiB
C
/** @file
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Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __OMAP3_DSS_GRAPHICS__
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#define __OMAP3_DSS_GRAPHICS__
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <Library/DebugLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/IoLib.h>
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#include <Protocol/DevicePathToText.h>
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#include <Protocol/EmbeddedExternalDevice.h>
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#include <Protocol/Cpu.h>
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#include <Guid/GlobalVariable.h>
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#include <Omap3530/Omap3530.h>
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#include <TPS65950.h>
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typedef struct {
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VENDOR_DEVICE_PATH Guid;
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EFI_DEVICE_PATH_PROTOCOL End;
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} LCD_GRAPHICS_DEVICE_PATH;
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typedef struct {
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UINTN Signature;
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EFI_HANDLE Handle;
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EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo;
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EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE Mode;
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EFI_GRAPHICS_OUTPUT_PROTOCOL Gop;
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LCD_GRAPHICS_DEVICE_PATH DevicePath;
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// EFI_EVENT ExitBootServicesEvent;
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} LCD_INSTANCE;
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#define LCD_INSTANCE_SIGNATURE SIGNATURE_32('l', 'c', 'd', '0')
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#define LCD_INSTANCE_FROM_GOP_THIS(a) CR (a, LCD_INSTANCE, Gop, LCD_INSTANCE_SIGNATURE)
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typedef struct {
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UINTN Mode;
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UINTN HorizontalResolution;
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UINTN VerticalResolution;
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UINT32 DssDivisor;
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UINT32 DispcDivisor;
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UINT32 HSync;
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UINT32 HFrontPorch;
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UINT32 HBackPorch;
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UINT32 VSync;
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UINT32 VFrontPorch;
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UINT32 VBackPorch;
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} LCD_MODE;
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EFI_STATUS
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InitializeDisplay (
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IN LCD_INSTANCE* Instance
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);
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EFI_STATUS
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EFIAPI
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LcdGraphicsQueryMode (
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IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
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IN UINT32 ModeNumber,
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OUT UINTN *SizeOfInfo,
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OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info
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);
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EFI_STATUS
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EFIAPI
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LcdGraphicsSetMode (
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IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
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IN UINT32 ModeNumber
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);
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EFI_STATUS
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EFIAPI
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LcdGraphicsBlt (
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IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
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IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL
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IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation,
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IN UINTN SourceX,
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IN UINTN SourceY,
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IN UINTN DestinationX,
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IN UINTN DestinationY,
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IN UINTN Width,
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IN UINTN Height,
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IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer
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);
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// HW registers
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#define CM_FCLKEN_DSS 0x48004E00
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#define CM_ICLKEN_DSS 0x48004E10
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#define DSS_CONTROL 0x48050040
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#define DSS_SYSCONFIG 0x48050010
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#define DSS_SYSSTATUS 0x48050014
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#define DISPC_CONTROL 0x48050440
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#define DISPC_CONFIG 0x48050444
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#define DISPC_SIZE_LCD 0x4805047C
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#define DISPC_TIMING_H 0x48050464
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#define DISPC_TIMING_V 0x48050468
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#define CM_CLKSEL_DSS 0x48004E40
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#define DISPC_DIVISOR 0x48050470
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#define DISPC_POL_FREQ 0x4805046C
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#define DISPC_GFX_TABLE_BA 0x480504B8
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#define DISPC_GFX_BA0 0x48050480
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#define DISPC_GFX_BA1 0x48050484
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#define DISPC_GFX_POS 0x48050488
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#define DISPC_GFX_SIZE 0x4805048C
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#define DISPC_GFX_ATTR 0x480504A0
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#define DISPC_GFX_PRELD 0x4805062C
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#define DISPC_DEFAULT_COLOR_0 0x4805044C
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//#define DISPC_IRQSTATUS
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// Bits
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#define EN_TV 0x4
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#define EN_DSS2 0x2
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#define EN_DSS1 0x1
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#define EN_DSS 0x1
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#define DSS_SOFTRESET 0x2
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#define DSS_RESETDONE 0x1
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#define BYPASS_MODE (BIT15 | BIT16)
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#define LCDENABLE BIT0
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#define ACTIVEMATRIX BIT3
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#define GOLCD BIT5
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#define DATALINES24 (BIT8 | BIT9)
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#define LCDENABLESIGNAL BIT28
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#define GFXENABLE BIT0
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#define RGB16 (0x6 << 1)
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#define BURSTSIZE16 (0x2 << 6)
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#define CLEARLOADMODE ~(BIT2 | BIT1)
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#define LOAD_FRAME_ONLY BIT2
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#endif
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