mirror of https://github.com/acidanthera/audk.git
101 lines
3.0 KiB
C
101 lines
3.0 KiB
C
/** @file
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Some configuration of QNC Package
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __INTEL_QNC_CONFIG_H__
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#define __INTEL_QNC_CONFIG_H__
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//
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// QNC Fixed configurations.
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//
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//
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// Memory arbiter fixed config values.
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//
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#define QNC_FIXED_CONFIG_ASTATUS ((UINT32) (\
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(ASTATUS_PRI_NORMAL << ASTATUS0_DEFAULT_BP) | \
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(ASTATUS_PRI_NORMAL << ASTATUS1_DEFAULT_BP) | \
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(ASTATUS_PRI_URGENT << ASTATUS0_RASISED_BP) | \
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(ASTATUS_PRI_URGENT << ASTATUS1_RASISED_BP) \
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))
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//
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// Memory Manager fixed config values.
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//
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#define V_DRAM_NON_HOST_RQ_LIMIT 2
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//
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// RMU Thermal config fixed config values for TS in Vref Mode.
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//
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#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_VREF_MODE 0x04
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#define V_TSCGF2_CONFIG2_ISPARECTRL_VREF_MODE 0x01
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#define V_TSCGF1_CONFIG_IBGEN_VREF_MODE 1
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#define V_TSCGF2_CONFIG_IDSCONTROL_VREF_MODE 0x011b
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#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_VREF_MODE 0x34
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//
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// RMU Thermal config fixed config values for TS in Ratiometric mode.
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//
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#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE 0x04
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#define V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE 0x02
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#define V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE 1
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#define V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE 0x011f
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#define V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE 0x0001
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#define V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE 0x01
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#define V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE 0x00
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#define V_TSCGF1_CONFIG_IBGEN_RATIO_MODE 0
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#define V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE 0
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#define V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE 0xC8
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#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE 0x17
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//
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// iCLK fixed config values.
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//
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#define V_MUXTOP_FLEX2 3
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#define V_MUXTOP_FLEX1 1
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//
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// PCIe Root Port fixed config values.
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//
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#define V_PCIE_ROOT_PORT_SBIC_VALUE (B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER)
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//
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// QNC structures for configuration.
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//
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typedef union {
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struct {
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UINT32 PortErrorMask :8;
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UINT32 SlotImplemented :1;
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UINT32 Reserved1 :1;
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UINT32 AspmEnable :1;
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UINT32 AspmAutoEnable :1;
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UINT32 AspmL0sEnable :2;
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UINT32 AspmL1Enable :1;
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UINT32 PmeInterruptEnable :1;
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UINT32 PhysicalSlotNumber :13;
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UINT32 Reserved2 :1;
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UINT32 PmSciEnable :1;
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UINT32 HotplugSciEnable :1;
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} Bits;
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UINT32 Uint32;
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} PCIEXP_ROOT_PORT_CONFIGURATION;
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typedef union {
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UINT32 Uint32;
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struct {
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UINT32 Pcie_0 :1; // 0: Disabled; 1: Enabled*
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UINT32 Pcie_1 :1; // 0: Disabled; 1: Enabled*
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UINT32 Smbus :1; // 0: Disabled; 1: Enabled*
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UINT32 Rsvd :29; // 0
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} Bits;
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} QNC_DEVICE_ENABLES;
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#endif
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