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BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Implements interfaces to read and write save state registers of AMD's processor family. Initializes processor SMMADDR and MASK depends on PcdSmrrEnable flag. Program or corrects the IP once control returns from SMM. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com>