mirror of https://github.com/acidanthera/audk.git
134 lines
3.2 KiB
Plaintext
134 lines
3.2 KiB
Plaintext
/** @file
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CPU T-state control methods
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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DefinitionBlock (
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"CPU0TST.aml",
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"SSDT",
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0x01,
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"SsgPmm",
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"Cpu0Tst",
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0x0013
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)
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{
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External (PDC0, IntObj)
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External (CFGD, FieldUnitObj)
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External(\_PR.CPU0, DeviceObj)
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External(_PSS)
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Scope(\_PR.CPU0)
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{
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Method(_TPC,0)
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{
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Return(ZERO) // Return All States Available.
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}
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Name(TPTC, ResourceTemplate()
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{
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Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC
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})
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//
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// If OSPM is capable of direct access to on demand throttling MSR,
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// we use MSR method;otherwise we use IO method.
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//
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//
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// PDCx[2] = Indicates whether OSPM is capable of direct access to
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// on demand throttling MSR.
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//
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Method(_PTC, 0)
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{
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If(And(PDC0, 0x0004))
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{
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Return(Package() // MSR Method
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{
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
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}
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)
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}
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Return(Package() // IO Method
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{
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//
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// PM IO base ("PMBALVL0" will be updated at runtime)
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//
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ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)},
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ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)}
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}
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)
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}
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//
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// _TSS returned package for IO Method
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//
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Name(TSSI, Package()
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{
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Package(){100, 1000, 0, 0x00, 0}
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}
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)
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//
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// _TSS returned package for MSR Method
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//
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Name(TSSM, Package()
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{
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Package(){100, 1000, 0, 0x00, 0}
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}
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)
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Method(_TSS, 0)
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{
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//
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// If OSPM is capable of direct access to on demand throttling MSR,
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// we report TSSM;otherwise report TSSI.
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//
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If(And(PDC0, 0x0004))
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{
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Return(TSSM)
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}
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Return(TSSI)
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}
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Method(_TSD, 0)
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{
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//
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// If CMP is suppored, we report the dependency with two processors
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//
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If(LAnd(And(CFGD, 0x1000000), LNot(And(PDC0, 4))))
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{
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Return(Package()
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{
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Package()
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{
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5, // # entries.
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0, // Revision.
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0, // Domain #.
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0xFD, // Coord Type- SW_ANY
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2 // # processors.
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}
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}
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)
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}
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//
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// Otherwise, we report the dependency with one processor
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//
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Return(Package()
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{
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Package()
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{
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5, // # entries.
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0, // Revision.
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0, // Domain #.
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0xFC, // Coord Type- SW_ALL
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1 // # processors.
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}
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}
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)
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}
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}
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}
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