mirror of https://github.com/acidanthera/audk.git
172 lines
7.1 KiB
Plaintext
172 lines
7.1 KiB
Plaintext
/** @file
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Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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Device(IOTD) {
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Name(_HID, "MSFT8000")
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Name(_CID, "MSFT8000")
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Name(_CRS, ResourceTemplate() {
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// Index 0
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SPISerialBus( // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI
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1, // Device selection
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PolarityLow, // Device selection polarity
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FourWireMode, // wiremode
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8, // databit len
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ControllerInitiated, // slave mode
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8000000, // Connection speed
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ClockPolarityLow, // Clock polarity
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ClockPhaseSecond, // clock phase
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"\\_SB.SPI1", // ResourceSource: SPI bus controller name
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0, // ResourceSourceIndex
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ResourceConsumer, // Resource usage
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JSPI, // DescriptorName: creates name for offset of resource descriptor
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) // Vendor Data
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// Index 1
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I2CSerialBus( // Pin 13, 15 of JP1, for SIO_I2C5 (signal)
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0x00, // SlaveAddress: bus address (TBD)
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, // SlaveMode: default to ControllerInitiated
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400000, // ConnectionSpeed: in Hz
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, // Addressing Mode: default to 7 bit
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"\\_SB.I2C6", // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))
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,
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,
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JI2C, // Descriptor Name: creates name for offset of resource descriptor
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) // VendorData
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// Index 2
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UARTSerialBus( // Pin 17, 19 of JP1, for SIO_UART2
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115200, // InitialBaudRate: in bits ber second
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, // BitsPerByte: default to 8 bits
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, // StopBits: Defaults to one bit
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0xfc, // LinesInUse: 8 1-bit flags to declare line enabled
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, // IsBigEndian: default to LittleEndian
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, // Parity: Defaults to no parity
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, // FlowControl: Defaults to no flow control
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32, // ReceiveBufferSize
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32, // TransmitBufferSize
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"\\_SB.URT2", // ResourceSource: UART bus controller name
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,
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,
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UAR2, // DescriptorName: creates name for offset of resource descriptor
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)
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// Index 3
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0} // Pin 21 of JP1 (GPIO_S5[00])
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// Index 4
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0}
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// Index 5
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1} // Pin 23 of JP1 (GPIO_S5[01])
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// Index 6
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}
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// Index 7
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2} // Pin 25 of JP1 (GPIO_S5[02])
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// Index 8
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2}
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// Index 9
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UARTSerialBus( // Pin 6, 8, 10, 12 of JP1, for SIO_UART1
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115200, // InitialBaudRate: in bits ber second
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, // BitsPerByte: default to 8 bits
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, // StopBits: Defaults to one bit
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0xfc, // LinesInUse: 8 1-bit flags to declare line enabled
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, // IsBigEndian: default to LittleEndian
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, // Parity: Defaults to no parity
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FlowControlHardware, // FlowControl: Defaults to no flow control
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32, // ReceiveBufferSize
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32, // TransmitBufferSize
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"\\_SB.URT1", // ResourceSource: UART bus controller name
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,
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,
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UAR1, // DescriptorName: creates name for offset of resource descriptor
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)
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// Index 10
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62} // Pin 14 of JP1 (GPIO_SC[62])
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// Index 11
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62}
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// Index 12
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63} // Pin 16 of JP1 (GPIO_SC[63])
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// Index 13
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63}
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// Index 14
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65} // Pin 18 of JP1 (GPIO_SC[65])
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// Index 15
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65}
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// Index 16
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64} // Pin 20 of JP1 (GPIO_SC[64])
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// Index 17
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64}
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// Index 18
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94} // Pin 22 of JP1 (GPIO_SC[94])
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// Index 19
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94}
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// Index 20
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95} // Pin 24 of JP1 (GPIO_SC[95])
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// Index 21
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95}
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// Index 22
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GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54} // Pin 26 of JP1 (GPIO_SC[54])
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// Index 23
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GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}
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})
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Name(_DSD, Package() {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package(1) { // Just one Property for IOT (at this time)
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Package(2) { //The <20>symbolic-identifiers<72> property
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"symbolic-identifiers",
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Package() { //Contains all the <resource index, symbolic-identifier> pairs
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0, "SPI0",
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1, "I2C5",
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2, "UART2",
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3, 21, // Pin 21 of JP1 (GPIO_S5[00])
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4, 21, // Pin 21 for separate resource.
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5, 23, // Pin 23 of JP1 (GPIO_S5[01])
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6, 23,
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7, 25, // Pin 25 of JP1 (GPIO_S5[02])
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8, 25,
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9, "UART1",
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10, 14, // Pin 14 of JP1 (GPIO_SC[62])
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11, 14,
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12, 16, // Pin 16 of JP1 (GPIO_SC[63])
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13, 16,
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14, 18, // Pin 18 of JP1 (GPIO_SC[65])
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15, 18,
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16, 20, // Pin 20 of JP1 (GPIO_SC[64])
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17, 20,
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18, 22, // Pin 22 of JP1 (GPIO_SC[94])
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19, 22,
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20, 24, // Pin 24 of JP1 (GPIO_SC[95])
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21, 24,
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22, 26, // Pin 26 of JP1 (GPIO_SC[54])
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23, 26
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}
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}
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}
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})
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Method(_STA,0,Serialized) {
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//
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// Only report IoT virtual device when all pins' configuration follows MSFT's datasheet.
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//
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If (LEqual(IOT, 1)) {
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Return (0xF)
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}
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Return (0x0)
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}
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}
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