mirror of https://github.com/acidanthera/audk.git
300 lines
7.9 KiB
NASM
300 lines
7.9 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; SmiEntry.nasm
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;
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; Abstract:
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;
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; Code template of the SMI handler for a particular processor
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;
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;-------------------------------------------------------------------------------
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%include "StuffRsbNasm.inc"
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%include "Nasm.inc"
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%define MSR_IA32_S_CET 0x6A2
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%define MSR_IA32_CET_SH_STK_EN 0x1
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%define MSR_IA32_CET_WR_SHSTK_EN 0x2
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%define MSR_IA32_CET_ENDBR_EN 0x4
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%define MSR_IA32_CET_LEG_IW_EN 0x8
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%define MSR_IA32_CET_NO_TRACK_EN 0x10
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%define MSR_IA32_CET_SUPPRESS_DIS 0x20
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%define MSR_IA32_CET_SUPPRESS 0x400
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%define MSR_IA32_CET_TRACKER 0x800
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%define MSR_IA32_PL0_SSP 0x6A4
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%define CR4_CET 0x800000
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%define MSR_IA32_MISC_ENABLE 0x1A0
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%define MSR_EFER 0xc0000080
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%define MSR_EFER_XD 0x800
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;
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; Constants relating to PROCESSOR_SMM_DESCRIPTOR
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;
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%define DSC_OFFSET 0xfb00
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%define DSC_GDTPTR 0x30
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%define DSC_GDTSIZ 0x38
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%define DSC_CS 14
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%define DSC_DS 16
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%define DSC_SS 18
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%define DSC_OTHERSEG 20
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%define PROTECT_MODE_CS 0x8
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%define PROTECT_MODE_DS 0x20
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%define TSS_SEGMENT 0x40
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extern ASM_PFX(SmiRendezvous)
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extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
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extern ASM_PFX(CpuSmmDebugEntry)
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extern ASM_PFX(CpuSmmDebugExit)
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global ASM_PFX(gcSmiHandlerTemplate)
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global ASM_PFX(gcSmiHandlerSize)
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global ASM_PFX(gPatchSmiCr3)
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global ASM_PFX(gPatchSmiStack)
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global ASM_PFX(gPatchSmbase)
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extern ASM_PFX(mXdSupported)
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global ASM_PFX(gPatchXdSupported)
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extern ASM_PFX(gSmiHandlerIdtr)
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extern ASM_PFX(mCetSupported)
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global ASM_PFX(mPatchCetSupported)
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global ASM_PFX(mPatchCetPl0Ssp)
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global ASM_PFX(mPatchCetInterruptSsp)
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SECTION .text
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BITS 16
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ASM_PFX(gcSmiHandlerTemplate):
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_SmiEntryPoint:
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mov bx, _GdtDesc - _SmiEntryPoint + 0x8000
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mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
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dec ax
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mov [cs:bx], ax
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mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
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mov [cs:bx + 2], eax
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mov ebp, eax ; ebp = GDT base
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o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
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mov ax, PROTECT_MODE_CS
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mov [cs:bx-0x2],ax
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mov edi, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmbase):
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lea eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]
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mov [cs:bx-0x6],eax
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mov ebx, cr0
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and ebx, 0x9ffafff3
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or ebx, 0x23
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mov cr0, ebx
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jmp dword 0x0:0x0
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_GdtDesc:
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DW 0
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DD 0
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BITS 32
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@32bit:
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mov ax, PROTECT_MODE_DS
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o16 mov ds, ax
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o16 mov es, ax
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o16 mov fs, ax
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o16 mov gs, ax
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o16 mov ss, ax
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mov esp, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmiStack):
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mov eax, ASM_PFX(gSmiHandlerIdtr)
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lidt [eax]
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jmp ProtFlatMode
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ProtFlatMode:
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmiCr3):
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mov cr3, eax
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;
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; Need to test for CR4 specific bit support
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;
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mov eax, 1
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cpuid ; use CPUID to determine if specific CR4 bits are supported
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xor eax, eax ; Clear EAX
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test edx, BIT2 ; Check for DE capabilities
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jz .0
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or eax, BIT3
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.0:
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test edx, BIT6 ; Check for PAE capabilities
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jz .1
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or eax, BIT5
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.1:
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test edx, BIT7 ; Check for MCE capabilities
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jz .2
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or eax, BIT6
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.2:
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test edx, BIT24 ; Check for FXSR capabilities
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jz .3
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or eax, BIT9
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.3:
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test edx, BIT25 ; Check for SSE capabilities
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jz .4
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or eax, BIT10
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.4: ; as cr4.PGE is not set here, refresh cr3
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mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
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cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0
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jz .6
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; Load TSS
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mov byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag
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mov eax, TSS_SEGMENT
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ltr ax
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.6:
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; enable NXE if supported
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mov al, strict byte 1 ; source operand may be patched
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ASM_PFX(gPatchXdSupported):
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cmp al, 0
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jz @SkipXd
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;
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; Check XD disable bit
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;
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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push edx ; save MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
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jz .5
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and dx, 0xFFFB ; clear XD Disable bit if it is set
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wrmsr
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.5:
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mov ecx, MSR_EFER
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rdmsr
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or ax, MSR_EFER_XD ; enable NXE
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wrmsr
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jmp @XdDone
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@SkipXd:
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sub esp, 4
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@XdDone:
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mov ebx, cr0
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or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
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mov cr0, ebx
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lea ebx, [edi + DSC_OFFSET]
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mov ax, [ebx + DSC_DS]
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mov ds, eax
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mov ax, [ebx + DSC_OTHERSEG]
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mov es, eax
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mov fs, eax
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mov gs, eax
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mov ax, [ebx + DSC_SS]
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mov ss, eax
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mov ebx, [esp + 4] ; ebx <- CpuIndex
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; enable CET if supported
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mov al, strict byte 1 ; source operand may be patched
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ASM_PFX(mPatchCetSupported):
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cmp al, 0
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jz CetDone
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mov ecx, MSR_IA32_S_CET
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rdmsr
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push edx
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push eax
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mov ecx, MSR_IA32_PL0_SSP
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rdmsr
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push edx
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push eax
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mov ecx, MSR_IA32_S_CET
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mov eax, MSR_IA32_CET_SH_STK_EN
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xor edx, edx
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wrmsr
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mov ecx, MSR_IA32_PL0_SSP
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(mPatchCetPl0Ssp):
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xor edx, edx
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wrmsr
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mov ecx, cr0
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btr ecx, 16 ; clear WP
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mov cr0, ecx
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mov [eax], eax ; reload SSP, and clear busyflag.
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xor ecx, ecx
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mov [eax + 4], ecx
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(mPatchCetInterruptSsp):
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cmp eax, 0
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jz CetInterruptDone
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mov [eax], eax ; reload SSP, and clear busyflag.
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xor ecx, ecx
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mov [eax + 4], ecx
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CetInterruptDone:
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mov ecx, cr0
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bts ecx, 16 ; set WP
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mov cr0, ecx
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mov eax, 0x668 | CR4_CET
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mov cr4, eax
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SETSSBSY
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CetDone:
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push ebx
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mov eax, ASM_PFX(CpuSmmDebugEntry)
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call eax
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add esp, 4
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push ebx
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mov eax, ASM_PFX(SmiRendezvous)
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call eax
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add esp, 4
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push ebx
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mov eax, ASM_PFX(CpuSmmDebugExit)
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call eax
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add esp, 4
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mov eax, ASM_PFX(mCetSupported)
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mov al, [eax]
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cmp al, 0
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jz CetDone2
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mov eax, 0x668
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mov cr4, eax ; disable CET
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mov ecx, MSR_IA32_PL0_SSP
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pop eax
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pop edx
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wrmsr
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mov ecx, MSR_IA32_S_CET
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pop eax
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pop edx
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wrmsr
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CetDone2:
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mov eax, ASM_PFX(mXdSupported)
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mov al, [eax]
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cmp al, 0
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jz .7
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pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2
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jz .7
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
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wrmsr
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.7:
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StuffRsb32
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rsm
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ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint
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global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)
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ASM_PFX(PiSmmCpuSmiEntryFixupAddress):
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ret
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