mirror of https://github.com/acidanthera/audk.git
464 lines
15 KiB
C
464 lines
15 KiB
C
/** @file
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Intel Processor Trace feature.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "CpuCommonFeatures.h"
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#define MAX_TOPA_ENTRY_COUNT 2
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///
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/// Processor trace buffer size selection.
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///
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typedef enum {
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Enum4K = 0,
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Enum8K,
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Enum16K,
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Enum32K,
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Enum64K,
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Enum128K,
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Enum256K,
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Enum512K,
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Enum1M,
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Enum2M,
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Enum4M,
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Enum8M,
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Enum16M,
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Enum32M,
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Enum64M,
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Enum128M,
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EnumProcTraceMemDisable
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} PROC_TRACE_MEM_SIZE;
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///
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/// Processor trace output scheme selection.
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///
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typedef enum {
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OutputSchemeSingleRange = 0,
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OutputSchemeToPA,
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OutputSchemeInvalid
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} PROC_TRACE_OUTPUT_SCHEME;
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typedef struct {
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BOOLEAN ProcTraceSupported;
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BOOLEAN TopaSupported;
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BOOLEAN SingleRangeSupported;
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} PROC_TRACE_PROCESSOR_DATA;
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typedef struct {
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UINT32 NumberOfProcessors;
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UINT8 ProcTraceOutputScheme;
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UINT32 ProcTraceMemSize;
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UINTN *ThreadMemRegionTable;
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UINTN AllocatedThreads;
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UINTN *TopaMemArray;
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UINTN TopaMemArrayCount;
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PROC_TRACE_PROCESSOR_DATA *ProcessorData;
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} PROC_TRACE_DATA;
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typedef struct {
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UINT64 TopaEntry[MAX_TOPA_ENTRY_COUNT];
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} PROC_TRACE_TOPA_TABLE;
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/**
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Prepares for the data used by CPU feature detection and initialization.
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@param[in] NumberOfProcessors The number of CPUs in the platform.
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@return Pointer to a buffer of CPU related configuration data.
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@note This service could be called by BSP only.
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**/
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VOID *
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EFIAPI
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ProcTraceGetConfigData (
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IN UINTN NumberOfProcessors
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)
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{
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PROC_TRACE_DATA *ConfigData;
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ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors);
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ASSERT (ConfigData != NULL);
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ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *) ((UINT8*) ConfigData + sizeof (PROC_TRACE_DATA));
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ConfigData->NumberOfProcessors = (UINT32) NumberOfProcessors;
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ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize);
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ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme);
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return ConfigData;
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}
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/**
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Detects if Intel Processor Trace feature supported on current
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processor.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
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structure for the CPU executing this function.
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@param[in] ConfigData A pointer to the configuration buffer returned
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by CPU_FEATURE_GET_CONFIG_DATA. NULL if
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CPU_FEATURE_GET_CONFIG_DATA was not provided in
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RegisterCpuFeature().
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@retval TRUE Processor Trace feature is supported.
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@retval FALSE Processor Trace feature is not supported.
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@note This service could be called by BSP/APs.
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**/
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BOOLEAN
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EFIAPI
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ProcTraceSupport (
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IN UINTN ProcessorNumber,
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IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
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IN VOID *ConfigData OPTIONAL
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)
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{
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PROC_TRACE_DATA *ProcTraceData;
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CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
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CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
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//
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// Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)
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//
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ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
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if ((ProcTraceData->ProcTraceMemSize >= EnumProcTraceMemDisable) ||
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(ProcTraceData->ProcTraceOutputScheme >= OutputSchemeInvalid)) {
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return FALSE;
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}
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//
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// Check if Processor Trace is supported
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//
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AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, &Ebx.Uint32, NULL, NULL);
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ProcTraceData->ProcessorData[ProcessorNumber].ProcTraceSupported = (BOOLEAN) (Ebx.Bits.IntelProcessorTrace == 1);
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if (!ProcTraceData->ProcessorData[ProcessorNumber].ProcTraceSupported) {
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return FALSE;
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}
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AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);
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ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1);
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ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1);
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if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported ||
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ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported) {
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return TRUE;
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}
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return FALSE;
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}
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/**
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Initializes Intel Processor Trace feature to specific state.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
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structure for the CPU executing this function.
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@param[in] ConfigData A pointer to the configuration buffer returned
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by CPU_FEATURE_GET_CONFIG_DATA. NULL if
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CPU_FEATURE_GET_CONFIG_DATA was not provided in
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RegisterCpuFeature().
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@param[in] State If TRUE, then the Processor Trace feature must be
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enabled.
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If FALSE, then the Processor Trace feature must be
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disabled.
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@retval RETURN_SUCCESS Intel Processor Trace feature is initialized.
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**/
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RETURN_STATUS
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EFIAPI
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ProcTraceInitialize (
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IN UINTN ProcessorNumber,
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IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
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IN VOID *ConfigData, OPTIONAL
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IN BOOLEAN State
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)
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{
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UINT64 MsrValue;
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UINT32 MemRegionSize;
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UINTN Pages;
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UINTN Alignment;
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UINTN MemRegionBaseAddr;
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UINTN *ThreadMemRegionTable;
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UINTN Index;
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UINTN TopaTableBaseAddr;
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UINTN AlignedAddress;
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UINTN *TopaMemArray;
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PROC_TRACE_TOPA_TABLE *TopaTable;
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PROC_TRACE_DATA *ProcTraceData;
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BOOLEAN FirstIn;
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ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
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MemRegionBaseAddr = 0;
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FirstIn = FALSE;
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if (ProcTraceData->ThreadMemRegionTable == NULL) {
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FirstIn = TRUE;
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DEBUG ((DEBUG_INFO, "Initialize Processor Trace\n"));
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}
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///
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/// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding
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///
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MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12));
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if (FirstIn) {
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DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));
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}
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//
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// Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CTL[0]==1b
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//
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MsrValue = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
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if ((MsrValue & BIT0) != 0) {
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///
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/// Clear bit 0 in MSR IA32_RTIT_CTL (570)
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///
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MsrValue &= (UINT64) ~BIT0;
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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MSR_IA32_RTIT_CTL,
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MsrValue
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);
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///
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/// Clear MSR IA32_RTIT_STS (571h) to all zeros
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///
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MsrValue = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
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MsrValue &= 0x0;
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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MSR_IA32_RTIT_STATUS,
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MsrValue
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);
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}
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if (FirstIn) {
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//
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// Let BSP allocate and create the necessary memory region (Aligned to the size of
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// the memory region from setup option(ProcTraceMemSize) which is an integral multiple of 4kB)
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// for the all the enabled threads for storing Processor Trace debug data. Then Configure the trace
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// address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be
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// aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 clear.
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//
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ThreadMemRegionTable = (UINTN *) AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));
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if (ThreadMemRegionTable == NULL) {
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DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));
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return RETURN_OUT_OF_RESOURCES;
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}
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ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable;
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for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) {
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Pages = EFI_SIZE_TO_PAGES (MemRegionSize);
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Alignment = MemRegionSize;
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AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);
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if (AlignedAddress == 0) {
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DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads));
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if (Index == 0) {
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//
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// Could not allocate for BSP even
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//
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FreePool ((VOID *) ThreadMemRegionTable);
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ThreadMemRegionTable = NULL;
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return RETURN_OUT_OF_RESOURCES;
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}
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break;
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}
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ThreadMemRegionTable[Index] = AlignedAddress;
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DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index]));
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}
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DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads));
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MemRegionBaseAddr = ThreadMemRegionTable[0];
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} else {
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if (ProcessorNumber < ProcTraceData->AllocatedThreads) {
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MemRegionBaseAddr = ProcTraceData->ThreadMemRegionTable[ProcessorNumber];
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} else {
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return RETURN_SUCCESS;
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}
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}
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///
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/// Check Processor Trace output scheme: Single Range output or ToPA table
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///
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//
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// Single Range output scheme
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//
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if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
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(ProcTraceData->ProcTraceOutputScheme == OutputSchemeSingleRange)) {
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if (FirstIn) {
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DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));
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}
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//
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// Clear MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)
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//
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MsrValue = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
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MsrValue &= (UINT64) ~BIT8;
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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MSR_IA32_RTIT_CTL,
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MsrValue
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);
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//
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// Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with the allocated Memory Region
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//
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MsrValue = (UINT64) MemRegionBaseAddr;
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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MSR_IA32_RTIT_OUTPUT_BASE,
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MsrValue
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);
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//
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// Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)
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//
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MsrValue = (UINT64) MemRegionSize - 1;
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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MSR_IA32_RTIT_OUTPUT_MASK_PTRS,
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MsrValue
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);
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}
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//
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// ToPA(Table of physical address) scheme
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//
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if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
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(ProcTraceData->ProcTraceOutputScheme == OutputSchemeToPA)) {
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//
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// Create ToPA structure aligned at 4KB for each logical thread
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// with at least 2 entries by 8 bytes size each. The first entry
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// should have the trace output base address in bits 47:12, 6:9
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// for Size, bits 4,2 and 0 must be cleared. The second entry
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// should have the base address of the table location in bits
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// 47:12, bits 4 and 2 must be cleared and bit 0 must be set.
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//
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if (FirstIn) {
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DEBUG ((DEBUG_INFO, "ProcTrace: Enabling ToPA scheme \n"));
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//
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// Let BSP allocate ToPA table mem for all threads
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//
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TopaMemArray = (UINTN *) AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));
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if (TopaMemArray == NULL) {
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DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"));
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return RETURN_OUT_OF_RESOURCES;
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}
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ProcTraceData->TopaMemArray = TopaMemArray;
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for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) {
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Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));
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Alignment = 0x1000;
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AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);
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if (AlignedAddress == 0) {
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if (Index < ProcTraceData->AllocatedThreads) {
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ProcTraceData->AllocatedThreads = Index;
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}
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DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocating ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads));
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if (Index == 0) {
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//
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// Could not allocate for BSP
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//
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FreePool ((VOID *) TopaMemArray);
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TopaMemArray = NULL;
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return RETURN_OUT_OF_RESOURCES;
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}
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break;
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}
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TopaMemArray[Index] = AlignedAddress;
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DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64) TopaMemArray[Index]));
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}
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DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads));
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//
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// BSP gets the first block
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//
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TopaTableBaseAddr = TopaMemArray[0];
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} else {
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//
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// Count for currently executing AP.
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//
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if (ProcessorNumber < ProcTraceData->AllocatedThreads) {
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TopaTableBaseAddr = ProcTraceData->TopaMemArray[ProcessorNumber];
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} else {
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return RETURN_SUCCESS;
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}
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}
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TopaTable = (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr;
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TopaTable->TopaEntry[0] = (UINT64) (MemRegionBaseAddr | ((ProcTraceData->ProcTraceMemSize) << 6)) & ~BIT0;
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TopaTable->TopaEntry[1] = (UINT64) TopaTableBaseAddr | BIT0;
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//
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// Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with ToPA base
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//
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MsrValue = (UINT64) TopaTableBaseAddr;
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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MSR_IA32_RTIT_OUTPUT_BASE,
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MsrValue
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);
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//
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// Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0
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//
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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MSR_IA32_RTIT_OUTPUT_MASK_PTRS,
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0x7F
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);
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//
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// Enable ToPA output scheme by enabling MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)
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//
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MsrValue = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
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MsrValue |= BIT8;
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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MSR_IA32_RTIT_CTL,
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MsrValue
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);
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}
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///
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/// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)
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///
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MsrValue = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
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MsrValue |= (UINT64) BIT0 + BIT2 + BIT3 + BIT13;
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if (!State) {
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MsrValue &= (UINT64) ~BIT0;
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}
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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MSR_IA32_RTIT_CTL,
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MsrValue
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);
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return RETURN_SUCCESS;
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}
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