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63 lines
1.4 KiB
C
63 lines
1.4 KiB
C
/** @file
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Copyright (c) 2024, Mikhail Krichanov. All rights reserved.
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SPDX-License-Identifier: BSD-3-Clause
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**/
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#include "DxeMain.h"
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#include <Register/Intel/ArchitecturalMsr.h>
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VOID
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EFIAPI
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InitializeMsr (
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VOID
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)
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{
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UINT64 Msr;
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IA32_CR4 Cr4;
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IA32_EFLAGS32 Eflags;
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UINT32 Ebx;
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UINT32 Edx;
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Ebx = 0;
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Edx = 0;
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//
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// Forbid supervisor-mode accesses to any user-mode pages.
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// SMEP and SMAP must be supported.
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//
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AsmCpuidEx (0x07, 0x0, NULL, &Ebx, NULL, NULL);
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//
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// SYSENTER and SYSEXIT must be also supported.
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//
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AsmCpuidEx (0x01, 0x0, NULL, NULL, NULL, &Edx);
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if (((Ebx & BIT20) != 0) && ((Ebx & BIT7) != 0) && ((Edx & BIT11) != 0)) {
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Cr4.UintN = AsmReadCr4 ();
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Cr4.Bits.SMAP = 1;
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Cr4.Bits.SMEP = 1;
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AsmWriteCr4 (Cr4.UintN);
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Eflags.UintN = AsmReadEflags ();
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Eflags.Bits.AC = 0;
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AsmWriteEflags (Eflags.UintN);
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} else {
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DEBUG ((DEBUG_ERROR, "Core: Failed to initialize MSRs for Ring3.\n"));
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ASSERT (FALSE);
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}
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//
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// Initialize MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_EIP and
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// MSR_IA32_SYSENTER_ESP for SYSENTER and SYSEXIT.
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//
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Msr = RING0_CODE32_SEL;
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AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr);
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Msr = (UINT64)(UINTN)CoreBootServices;
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AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
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Msr = (UINT64)(UINTN)gCoreSysCallStackTop;
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AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
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}
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