audk/UefiCpuPkg
Laszlo Ersek 9f75aacc7a UefiCpuPkg/ResetVector/Vtf0: document segment register setup
"Main.asm" calls TransitionFromReal16To32BitFlat (and does some other
things) before it jumps to the platform's SEC entry point.

TransitionFromReal16To32BitFlat enters big real mode, and sets the DS, ES,
FS, GS, and SS registers to offset ("selector") LINEAR_SEL in the GDT
(defined in "UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm"). The
GDT entry ("segment descriptor") at LINEAR_SEL defines a segment covering
the full 32-bit address space, meant for "read/write data".

Document this fact for all the affected segment registers, as output
parameters for TransitionFromReal16To32BitFlat, saying "Selector allowing
flat access to all addresses".

For 64-bit SEC, "Main.asm" calls Transition32FlatTo64Flat in addition,
between calling TransitionFromReal16To32BitFlat and jumping to the SEC
entry point. Transition32FlatTo64Flat enters long mode. In long mode,
segmentation is largely ignored:

- all segments are considered flat (covering the whole 64-bit address
  space),

- with the (possible) exception of FS and GS, whose bases can still be
  changed, albeit with new methods, not through the GDT. (Through the
  IA32_FS_BASE and IA32_GS_BASE Model Specific Registers, and/or the
  WRFSBASE, WRGSBASE and SWAPGS instructions.)

Thus, document the segment registers with the same "Selector allowing flat
access to all addresses" language on the "Main.asm" level too, since that
is valid for both 32-bit and 64-bit modes.

(Technically, "Main.asm" does not return, but RBP/EBP, passed similarly to
the SEC entry point, is already documented as an output parameter.)

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Suggested-by: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-11-17 18:11:58 +01:00
..
Application/Cpuid UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016) 2016-12-16 11:48:21 +08:00
CpuDxe UefiCpuPkg/CpuDxe: Reduce debug message 2017-11-17 11:03:12 +08:00
CpuFeatures UefiCpuPkg/CpuFeatures: Export HOB if CPU initialized in PEI 2017-10-27 09:34:37 +08:00
CpuIo2Dxe UefiCpuPkg: Refine casting expression result to bigger size 2017-03-06 14:33:26 +08:00
CpuIo2Smm UefiCpuPkg: Refine casting expression result to bigger size 2017-03-06 14:33:26 +08:00
CpuIoPei UefiCpuPkg: Modify CpuIoPei to support new IoLib library 2017-01-17 10:10:32 +08:00
CpuMpPei UefiCpuPkg CpuMpPei: Update return status to follow spec. 2017-07-07 08:54:11 +08:00
CpuS3DataDxe UefiCpuPkg/CpuS3DataDxe: Consume the existing PcdCpuS3DataAddress 2017-03-22 10:11:25 +08:00
Feature/Capsule UefiCpuPkg/MicrocodeUpdate: Add MP support. 2016-12-28 15:09:02 +08:00
Include UefiCpuPkg/MtrrLib: Make comments align with function 2017-10-24 09:14:17 +08:00
Library UefiCpuPkg/MpInitLib:Make function comments align with function 2017-11-02 09:24:05 +08:00
PiSmmCommunication UefiCpuPkg PiSmmCommunicationSmm: Deprecate SMM Communication ACPI Table 2017-07-27 14:08:09 +08:00
PiSmmCpuDxeSmm UefiCpuPkg/PiSmmCpuDxeSmm: Add SmmMemoryAttribute protocol 2017-11-17 11:03:18 +08:00
ResetVector UefiCpuPkg/ResetVector/Vtf0: document segment register setup 2017-11-17 18:11:58 +01:00
SecCore UefiCpuPkg SecCore: Fix operands of different size in bitwise operation 2017-08-02 18:21:54 +08:00
Universal/Acpi/S3Resume2Pei UefiCpuPkg/S3Resume2Pei: Handle Communicate Ppi not exist issue. 2017-10-13 13:12:00 +08:00
UefiCpuPkg.dec UefiCpuPkg: Update default for PcdCpuProcTraceMemSize/PcdCpuProcTraceOutputScheme. 2017-08-28 15:13:49 +08:00
UefiCpuPkg.dsc UefiCpuPkg: Update package version to 0.80 2017-05-08 13:31:00 +08:00
UefiCpuPkg.uni UefiCpuPkg: Update default for PcdCpuProcTraceMemSize/PcdCpuProcTraceOutputScheme. 2017-08-28 15:13:49 +08:00
UefiCpuPkgExtra.uni UefiCpuPkg: Convert all .uni files to utf-8 2015-12-15 04:59:14 +00:00