mirror of https://github.com/acidanthera/audk.git
279 lines
12 KiB
C
279 lines
12 KiB
C
/** @file
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* SMSC LAN91x series Network Controller Driver.
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*
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* Copyright (c) 2013-2017 Linaro.org
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*
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* This program and the accompanying materials are licensed and
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* made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license
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* may be found at: http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __LAN91XDXEHW_H__
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#define __LAN91XDXEHW_H__
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#include <Base.h>
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#define MakeRegister(Bank, Offset) (((Bank) << 8) | (Offset))
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#define RegisterToBank(Register) (((Register) >> 8) & 0x07)
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#define RegisterToOffset(Register) ((Register) & 0x0f)
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/*---------------------------------------------------------------------------------------------------------------------
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SMSC LAN91x Registers
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---------------------------------------------------------------------------------------------------------------------*/
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#define LAN91X_BANK_OFFSET 0xe // Bank Select Register (all banks)
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#define LAN91X_TCR MakeRegister (0, 0x0) // Transmit Control Register
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#define LAN91X_EPHSR MakeRegister (0, 0x2) // EPH Status Register
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#define LAN91X_RCR MakeRegister (0, 0x4) // Receive Control Register
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#define LAN91X_ECR MakeRegister (0, 0x6) // Counter Register
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#define LAN91X_MIR MakeRegister (0, 0x8) // Memory Information Register
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#define LAN91X_RPCR MakeRegister (0, 0xa) // Receive/Phy Control Register
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#define LAN91X_CR MakeRegister (1, 0x0) // Configuration Register
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#define LAN91X_BAR MakeRegister (1, 0x2) // Base Address Register
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#define LAN91X_IAR0 MakeRegister (1, 0x4) // Individual Address Register 0
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#define LAN91X_IAR1 MakeRegister (1, 0x5) // Individual Address Register 1
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#define LAN91X_IAR2 MakeRegister (1, 0x6) // Individual Address Register 2
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#define LAN91X_IAR3 MakeRegister (1, 0x7) // Individual Address Register 3
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#define LAN91X_IAR4 MakeRegister (1, 0x8) // Individual Address Register 4
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#define LAN91X_IAR5 MakeRegister (1, 0x9) // Individual Address Register 5
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#define LAN91X_GPR MakeRegister (1, 0xa) // General Purpose Register
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#define LAN91X_CTR MakeRegister (1, 0xc) // Control Register
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#define LAN91X_MMUCR MakeRegister (2, 0x0) // MMU Command Register
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#define LAN91X_PNR MakeRegister (2, 0x2) // Packet Number Register
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#define LAN91X_ARR MakeRegister (2, 0x3) // Allocation Result Register
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#define LAN91X_FIFO MakeRegister (2, 0x4) // FIFO Ports Register
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#define LAN91X_PTR MakeRegister (2, 0x6) // Pointer Register
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#define LAN91X_DATA0 MakeRegister (2, 0x8) // Data Register 0
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#define LAN91X_DATA1 MakeRegister (2, 0x9) // Data Register 1
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#define LAN91X_DATA2 MakeRegister (2, 0xa) // Data Register 2
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#define LAN91X_DATA3 MakeRegister (2, 0xb) // Data Register 3
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#define LAN91X_IST MakeRegister (2, 0xc) // Interrupt Status Register
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#define LAN91X_MSK MakeRegister (2, 0xd) // Interrupt Mask Register
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#define LAN91X_MT0 MakeRegister (3, 0x0) // Multicast Table Register 0
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#define LAN91X_MT1 MakeRegister (3, 0x1) // Multicast Table Register 1
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#define LAN91X_MT2 MakeRegister (3, 0x2) // Multicast Table Register 2
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#define LAN91X_MT3 MakeRegister (3, 0x3) // Multicast Table Register 3
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#define LAN91X_MT4 MakeRegister (3, 0x4) // Multicast Table Register 4
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#define LAN91X_MT5 MakeRegister (3, 0x5) // Multicast Table Register 5
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#define LAN91X_MT6 MakeRegister (3, 0x6) // Multicast Table Register 6
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#define LAN91X_MT7 MakeRegister (3, 0x7) // Multicast Table Register 7
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#define LAN91X_MGMT MakeRegister (3, 0x8) // Management Interface Register
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#define LAN91X_REV MakeRegister (3, 0xa) // Revision Register
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#define LAN91X_RCV MakeRegister (3, 0xc) // RCV Register
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// Transmit Control Register Bits
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#define TCR_TXENA BIT0
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#define TCR_LOOP BIT1
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#define TCR_FORCOL BIT2
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#define TCR_PAD_EN BIT7
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#define TCR_NOCRC BIT8
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#define TCR_MON_CSN BIT10
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#define TCR_FDUPLX BIT11
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#define TCR_STP_SQET BIT12
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#define TCR_EPH_LOOP BIT13
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#define TCR_SWFDUP BIT15
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#define TCR_DEFAULT (TCR_TXENA | TCR_PAD_EN)
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#define TCR_CLEAR 0x0
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// EPH Status Register Bits
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#define EPHSR_TX_SUC BIT0
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#define EPHSR_SNGLCOL BIT1
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#define EPHSR_MULCOL BIT2
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#define EPHSR_LTX_MULT BIT3
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#define EPHSR_16COL BIT4
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#define EPHSR_SQET BIT5
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#define EPHSR_LTX_BRD BIT6
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#define EPHSR_TX_DEFR BIT7
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#define EPHSR_LATCOL BIT9
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#define EPHSR_LOST_CARR BIT10
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#define EPHSR_EXC_DEF BIT11
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#define EPHSR_CTR_ROL BIT12
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#define EPHSR_LINK_OK BIT14
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// Receive Control Register Bits
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#define RCR_RX_ABORT BIT0
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#define RCR_PRMS BIT1
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#define RCR_ALMUL BIT2
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#define RCR_RXEN BIT8
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#define RCR_STRIP_CRC BIT9
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#define RCR_ABORT_ENB BIT13
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#define RCR_FILT_CAR BIT14
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#define RCR_SOFT_RST BIT15
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#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
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#define RCR_CLEAR 0x0
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// Receive/Phy Control Register Bits
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#define RPCR_LS0B BIT2
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#define RPCR_LS1B BIT3
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#define RPCR_LS2B BIT4
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#define RPCR_LS0A BIT5
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#define RPCR_LS1A BIT6
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#define RPCR_LS2A BIT7
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#define RPCR_ANEG BIT11
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#define RPCR_DPLX BIT12
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#define RPCR_SPEED BIT13
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// Configuration Register Bits
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#define CR_EXT_PHY BIT9
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#define CR_GPCNTRL BIT10
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#define CR_NO_WAIT BIT12
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#define CR_EPH_POWER_EN BIT15
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#define CR_DEFAULT (CR_EPH_POWER_EN | CR_NO_WAIT)
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// Control Register Bits
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#define CTR_STORE BIT0
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#define CTR_RELOAD BIT1
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#define CTR_EEPROM_SEL BIT2
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#define CTR_TE_ENABLE BIT5
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#define CTR_CR_ENABLE BIT6
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#define CTR_LE_ENABLE BIT7
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#define CTR_AUTO_REL BIT11
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#define CTR_RCV_BAD BIT14
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#define CTR_RESERVED (BIT12 | BIT9 | BIT4)
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#define CTR_DEFAULT (CTR_RESERVED | CTR_AUTO_REL)
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// MMU Command Register Bits
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#define MMUCR_BUSY BIT0
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// MMU Command Register Operaction Codes
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#define MMUCR_OP_NOOP (0 << 5) // No operation
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#define MMUCR_OP_TX_ALLOC (1 << 5) // Allocate memory for TX
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#define MMUCR_OP_RESET_MMU (2 << 5) // Reset MMU to initial state
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#define MMUCR_OP_RX_POP (3 << 5) // Remove frame from top of RX FIFO
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#define MMUCR_OP_RX_POP_REL (4 << 5) // Remove and release frame from top of RX FIFO
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#define MMUCR_OP_RX_REL (5 << 5) // Release specific RX frame
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#define MMUCR_OP_TX_PUSH (6 << 5) // Enqueue packet number into TX FIFO
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#define MMUCR_OP_TX_RESET (7 << 5) // Reset TX FIFOs
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// Packet Number Register Bits
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#define PNR_PACKET (0x3f)
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// Allocation Result Register Bits
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#define ARR_PACKET (0x3f)
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#define ARR_FAILED BIT7
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// FIFO Ports Register Bits
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#define FIFO_TX_PACKET (0x003f)
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#define FIFO_TEMPTY BIT7
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#define FIFO_RX_PACKET (0x3f00)
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#define FIFO_REMPTY BIT15
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// Pointer Register Bits
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#define PTR_POINTER (0x07ff)
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#define PTR_NOT_EMPTY BIT11
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#define PTR_READ BIT13
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#define PTR_AUTO_INCR BIT14
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#define PTR_RCV BIT15
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// Interupt Status and Mask Register Bits
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#define IST_RCV BIT0
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#define IST_TX BIT1
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#define IST_TX_EMPTY BIT2
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#define IST_ALLOC BIT3
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#define IST_RX_OVRN BIT4
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#define IST_EPH BIT5
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#define IST_MD BIT7
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// Management Interface
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#define MGMT_MDO BIT0
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#define MGMT_MDI BIT1
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#define MGMT_MCLK BIT2
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#define MGMT_MDOE BIT3
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#define MGMT_MSK_CRS100 BIT14
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// RCV Register
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#define RCV_MBO (0x1f)
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#define RCV_RCV_DISCRD BIT7
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// Packet RX Status word bits
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#define RX_MULTICAST BIT0
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#define RX_HASH (0x7e)
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#define RX_TOO_SHORT BIT10
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#define RX_TOO_LONG BIT11
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#define RX_ODD_FRAME BIT12
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#define RX_BAD_CRC BIT13
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#define RX_BROADCAST BIT14
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#define RX_ALGN_ERR BIT15
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// Packet Byte Count word bits
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#define BCW_COUNT (0x7fe)
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// Packet Control Word bits
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#define PCW_ODD_BYTE (0x00ff)
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#define PCW_CRC BIT12
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#define PCW_ODD BIT13
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/*---------------------------------------------------------------------------------------------------------------------
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SMSC PHY Registers
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Most of these should be common, as there is
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documented STANDARD for PHY registers!
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---------------------------------------------------------------------------------------------------------------------*/
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//
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// PHY Register Numbers
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//
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#define PHY_INDEX_BASIC_CTRL 0
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#define PHY_INDEX_BASIC_STATUS 1
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#define PHY_INDEX_ID1 2
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#define PHY_INDEX_ID2 3
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#define PHY_INDEX_AUTO_NEG_ADVERT 4
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#define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5
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#define PHY_INDEX_CONFIG1 16
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#define PHY_INDEX_CONFIG2 17
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#define PHY_INDEX_STATUS_OUTPUT 18
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#define PHY_INDEX_MASK 19
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// PHY control register bits
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#define PHYCR_COLL_TEST BIT7 // Collision test enable
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#define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode
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#define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities
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#define PHYCR_PD BIT11 // Power-Down switch
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#define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable
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#define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
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#define PHYCR_LOOPBK BIT14 // Set loopback mode
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#define PHYCR_RESET BIT15 // Do a PHY reset
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// PHY status register bits
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#define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability
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#define PHYSTS_JABBER BIT1 // Jabber condition detected
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#define PHYSTS_LINK_STS BIT2 // Link Status
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#define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability
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#define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected
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#define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed
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#define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability
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#define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability
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#define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
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#define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability
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#define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
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// PHY Auto-Negotiation advertisement
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#define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector
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#define PHYANA_CSMA BIT0 // Advertise CSMA capability
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#define PHYANA_10BASET BIT5 // Advertise 10BASET capability
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#define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability
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#define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability
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#define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability
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#define PHYANA_100BASET4 BIT9 // Advertise 100 BASETX Full duplex capability
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#define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability
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#define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
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#endif /* __LAN91XDXEHW_H__ */
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