mirror of https://github.com/acidanthera/audk.git
179 lines
5.3 KiB
ArmAsm
179 lines
5.3 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# SmiException.S
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#
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# Abstract:
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#
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# Exception handlers used in SM mode
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#
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(gcStmPsd)
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ASM_GLOBAL ASM_PFX(SmmStmExceptionHandler)
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ASM_GLOBAL ASM_PFX(SmmStmSetup)
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ASM_GLOBAL ASM_PFX(SmmStmTeardown)
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.equ CODE_SEL, 0x38
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.equ DATA_SEL, 0x20
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.equ TR_SEL, 0x40
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.equ MSR_IA32_MISC_ENABLE, 0x1A0
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.equ MSR_EFER, 0x0c0000080
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.equ MSR_EFER_XD, 0x0800
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.data
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#
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# This structure serves as a template for all processors.
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#
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ASM_PFX(gcStmPsd):
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.ascii "TXTPSSIG"
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.word PSD_SIZE
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.word 1 # Version
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.long 0 # LocalApicId
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.byte 0xF # Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
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.byte 0 # BIOS to STM
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.byte 0 # STM to BIOS
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.byte 0
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.word CODE_SEL
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.word DATA_SEL
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.word DATA_SEL
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.word DATA_SEL
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.word TR_SEL
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.word 0
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.quad 0 # SmmCr3
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.quad ASM_PFX(_OnStmSetup)
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.quad ASM_PFX(_OnStmTeardown)
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.quad 0 # SmmSmiHandlerRip - SMM guest entrypoint
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.quad 0 # SmmSmiHandlerRsp
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.quad 0
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.long 0
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.long 0x80010100 # RequiredStmSmmRevId
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.quad ASM_PFX(_OnException)
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.quad 0 # ExceptionStack
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.word DATA_SEL
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.word 0x1F # ExceptionFilter
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.long 0
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.quad 0
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.quad 0 # BiosHwResourceRequirementsPtr
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.quad 0 # AcpiRsdp
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.byte 0 # PhysicalAddressBits
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.equ PSD_SIZE, . - ASM_PFX(gcStmPsd)
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.text
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#------------------------------------------------------------------------------
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# SMM Exception handlers
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(_OnException)
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ASM_PFX(_OnException):
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movq %rsp, %rcx
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subq $0x28, %rsp
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call ASM_PFX(SmmStmExceptionHandler)
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addq $0x28, %rsp
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movl %eax, %ebx
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movl $4, %eax
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.byte 0xf, 0x1, 0xc1 # VMCALL
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jmp .
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ASM_GLOBAL ASM_PFX(_OnStmSetup)
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ASM_PFX(_OnStmSetup):
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#
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# Check XD disable bit
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#
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xorq %r8, %r8
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movabsq $ASM_PFX(gStmXdSupported), %rax
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movb (%rax), %al
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cmpb $0, %al
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jz StmXdDone1
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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movq %rdx, %r8 # save MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
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jz L13
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andw $0x0FFFB, %dx # clear XD Disable bit if it is set
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wrmsr
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L13:
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movl $MSR_EFER, %ecx
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rdmsr
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orw $MSR_EFER_XD,%ax # enable NXE
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wrmsr
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StmXdDone1:
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pushq %r8
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subq $0x20, %rsp
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call ASM_PFX(SmmStmSetup)
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addq 0x20, %rsp
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movabsq $ASM_PFX(gStmXdSupported), %rax
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movb (%rax), %al
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cmpb $0, %al
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jz L14
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popq %rdx # get saved MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx
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jz L14
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
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wrmsr
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L14:
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rsm
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ASM_GLOBAL ASM_PFX(_OnStmTeardown)
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ASM_PFX(_OnStmTeardown):
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#
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# Check XD disable bit
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#
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xorq %r8, %r8
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movabsq $ASM_PFX(gStmXdSupported), %rax
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movb (%rax), %al
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cmpb $0, %al
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jz StmXdDone2
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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movq %rdx, %r8 # save MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
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jz L15
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andw $0x0FFFB, %dx # clear XD Disable bit if it is set
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wrmsr
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L15:
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movl $MSR_EFER, %ecx
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rdmsr
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orw $MSR_EFER_XD,%ax # enable NXE
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wrmsr
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StmXdDone2:
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pushq %r8
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subq $0x20, %rsp
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call ASM_PFX(SmmStmTeardown)
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addq $0x20, %rsp
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movabsq $ASM_PFX(gStmXdSupported), %rax
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movb (%rax), %al
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cmpb $0, %al
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jz L16
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popq %rdx # get saved MSR_IA32_MISC_ENABLE[63-32]
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testl $BIT2, %edx
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jz L16
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movl $MSR_IA32_MISC_ENABLE, %ecx
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rdmsr
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orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
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wrmsr
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L16:
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rsm
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