mirror of https://github.com/acidanthera/audk.git
439 lines
12 KiB
C
439 lines
12 KiB
C
/*++
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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PlatformInfo.h
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Abstract:
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GUID used for Platform Info Data entries in the HOB list.
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--*/
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#ifndef _PLATFORM_INFO_GUID_H_
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#define _PLATFORM_INFO_GUID_H_
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#ifndef ECP_FLAG
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#include <PiPei.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/SmbusLib.h>
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#include <IndustryStandard/SmBus.h>
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#endif
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#define PLATFORM_INFO_REVISION = 1 // Revision id for current platform information struct.
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//
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// Start::BayLake Board Defines
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//
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#define BOARD_REVISION_DEFAULT = 0xff
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#define UNKNOWN_FABID 0x0F
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#define FAB_ID_MASK 0x0F
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#define BOARD_ID_2 0x01
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#define BOARD_ID_1 0x40
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#define BOARD_ID_0 0x04
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#define BOARD_ID_DT_CRB 0x0
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#define BOARD_ID_DT_VLVR 0x1
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#define BOARD_ID_SVP_VLV 0xC
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#define BOARD_ID_SVP_EV_VLV 0xD
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//
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// End::BayLake Board Defines
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//
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//
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// Start::Alpine Valley Board Defines
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//
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#define DC_ID_DDR3L 0x00
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#define DC_ID_DDR3 0x04
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#define DC_ID_LPDDR3 0x02
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#define DC_ID_LPDDR2 0x06
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#define DC_ID_DDR4 0x01
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#define DC_ID_DDR3L_ECC 0x05
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#define DC_ID_NO_MEM 0x07
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//
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// End::Alpine Valley Board Defines
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//
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#define MAX_FAB_ID_RETRY_COUNT 100
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#define MAX_FAB_ID_CHECK_COUNT 3
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#define PLATFORM_INFO_HOB_REVISION 0x1
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#define EFI_PLATFORM_INFO_GUID \
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{ \
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0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \
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}
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extern EFI_GUID gEfiPlatformInfoGuid;
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typedef enum {
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FlavorUnknown = 0,
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//
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// Mobile
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//
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FlavorMobile = 1,
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//
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// Desktop
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//
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FlavorDesktop = 2,
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//
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// Tablet
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//
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FlavorTablet = 3
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} PLATFORM_FLAVOR;
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#pragma pack(1)
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typedef struct {
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UINT16 PciResourceIoBase;
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UINT16 PciResourceIoLimit;
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UINT32 PciResourceMem32Base;
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UINT32 PciResourceMem32Limit;
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UINT64 PciResourceMem64Base;
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UINT64 PciResourceMem64Limit;
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UINT64 PciExpressBase;
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UINT32 PciExpressSize;
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UINT8 PciHostAddressWidth;
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UINT8 PciResourceMinSecBus;
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} EFI_PLATFORM_PCI_DATA;
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typedef struct {
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UINT8 CpuAddressWidth;
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UINT32 CpuFamilyStepping;
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} EFI_PLATFORM_CPU_DATA;
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typedef struct {
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UINT8 SysIoApicEnable;
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UINT8 SysSioExist;
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} EFI_PLATFORM_SYS_DATA;
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typedef struct {
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UINT32 MemTolm;
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UINT32 MemMaxTolm;
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UINT32 MemTsegSize;
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UINT32 MemTsegBase;
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UINT32 MemIedSize;
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UINT32 MemIgdSize;
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UINT32 MemIgdBase;
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UINT32 MemIgdGttSize;
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UINT32 MemIgdGttBase;
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UINT64 MemMir0;
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UINT64 MemMir1;
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UINT32 MemConfigSize;
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UINT16 MmioSize;
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UINT8 DdrFreq;
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UINT8 DdrType;
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UINT32 MemSize;
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BOOLEAN EccSupport;
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UINT8 Reserved[3];
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UINT16 DimmSize[2];
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} EFI_PLATFORM_MEM_DATA;
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typedef struct {
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UINT32 IgdOpRegionAddress; // IGD OpRegion Starting Address
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UINT8 IgdBootType; // IGD Boot Display Device
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UINT8 IgdPanelType; // IGD Panel Type CMOs option
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UINT8 IgdTvFormat; // IGD TV Format CMOS option
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UINT8 IgdTvMinor; // IGD TV Minor Format CMOS option
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UINT8 IgdPanelScaling; // IGD Panel Scaling
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UINT8 IgdBlcConfig; // IGD BLC Configuration
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UINT8 IgdBiaConfig; // IGD BIA Configuration
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UINT8 IgdSscConfig; // IGD SSC Configuration
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UINT8 IgdDvmtMemSize; // IGD DVMT Memory Size
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UINT8 IgdFunc1Enable; // IGD Function 1 Enable
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UINT8 IgdHpllVco; // HPLL VCO
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UINT8 IgdSciSmiMode; // GMCH SMI/SCI mode (0=SCI)
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UINT8 IgdPAVP; // IGD PAVP data
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} EFI_PLATFORM_IGD_DATA;
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typedef enum {
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BOARD_ID_AV_SVP = 0x0, // Alpine Valley Board
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BOARD_ID_BL_RVP = 0x2, // BayLake Board (RVP)
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BOARD_ID_BL_FFRD8 = 0x3, // FFRD8 b'0011
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BOARD_ID_BL_FFRD = 0x4, // BayLake Board (FFRD)
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BOARD_ID_BL_RVP_DDR3L = 0x5, // BayLake Board (RVP DDR3L)
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BOARD_ID_BL_STHI = 0x7, // PPV- STHI Board
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BOARD_ID_BB_RVP = 0x20, // Bayley Bay Board
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BOARD_ID_BS_RVP = 0x30, // Bakersport Board
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BOARD_ID_CVH = 0x90, // Crestview Hills
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BOARD_ID_MINNOW2 = 0xA0, // MinnowBorad Max
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BOARD_ID_MINNOW2_TURBOT = 0xB0 // MinnowBoard Turbot
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} BOARD_ID_LIST;
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typedef enum {
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FAB1 = 0,
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FAB2 = 1,
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FAB3 = 2
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} FAB_ID_LIST;
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typedef enum {
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PR0 = 0, // FFRD PR0
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PR05 = 1, // FFRD PR0.3 and PR 0.5
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PR1 = 2, // FFRD PR1
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PR11 = 3 // FFRD PR1.1
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} FFRD_ID_LIST;
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//
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// VLV2 GPIO GROUP OFFSET
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//
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#define GPIO_SCORE_OFFSET 0x0000
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#define GPIO_NCORE_OFFSET 0x1000
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#define GPIO_SSUS_OFFSET 0x2000
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//
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// GPIO Initialization Data Structure for BayLake.
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// SC = SCORE, SS= SSUS
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// Note: NC doesn't support GPIO functionality in IO access mode, only support in MMIO access mode.
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//
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//
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// IO space
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//
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typedef struct{
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UINT32 Use_Sel_SC0;
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UINT32 Use_Sel_SC1;
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UINT32 Use_Sel_SC2;
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UINT32 Use_Sel_SS;
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UINT32 Io_Sel_SC0;
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UINT32 Io_Sel_SC1;
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UINT32 Io_Sel_SC2;
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UINT32 Io_Sel_SS;
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UINT32 GP_Lvl_SC0;
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UINT32 GP_Lvl_SC1;
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UINT32 GP_Lvl_SC2;
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UINT32 GP_Lvl_SS;
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UINT32 TPE_SC0;
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UINT32 TPE_SS;
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UINT32 TNE_SC0;
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UINT32 TNE_SS;
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UINT32 TS_SC0;
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UINT32 TS_SS;
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UINT32 WE_SS;
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} CFIO_INIT_STRUCT;
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//
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// CFIO PAD configuration Registers
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//
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//
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// Memory space
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//
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typedef union {
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UINT32 dw;
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struct {
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UINT32 Func_Pin_Mux:3; // 0:2 Function of CFIO selection
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UINT32 ipslew:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width
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UINT32 inslew:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate
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UINT32 Pull_assign:2; // 7:8 Pull assignment
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UINT32 Pull_strength:2; // 9:10 Pull strength
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UINT32 Bypass_flop:1; // 11 Bypass flop
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UINT32 Filter_en:1; // 12 Filter Enable
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UINT32 Hist_ctrl:2; // 13:14 hysteresis control
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UINT32 Hist_enb:1; // 15 Hysteresis enable, active low
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UINT32 Delay_line:6; // 16:21 Delay line values - Delay values for input or output
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UINT32 Reserved:3; // 22:24 Reserved
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UINT32 TPE:1; // 25 Trigger Positive Edge Enable
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UINT32 TNE:1; // 26 Trigger Negative Edge Enable
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UINT32 Reserved2:3; // 27:29 Reserved
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UINT32 i1p5sel:1; // 30
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UINT32 IODEN:1; // 31 : Open Drain enable. Active high
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} r;
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} PAD_CONF0;
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typedef union{
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UINT32 dw;
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struct {
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UINT32 instr:16; // 0:15 Pad (N) strength.
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UINT32 ipstr:16; // 16:31 Pad (P) strength.
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}r;
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} PAD_CONF1;
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typedef union{
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UINT32 dw;
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struct {
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UINT32 pad_val:1; // 0 These registers are implemented as dual read/write with dedicated storage each.
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UINT32 ioutenb:1; // 1 output enable
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UINT32 iinenb:1; // 2 input enable
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UINT32 Reserved:29; // 3:31 Reserved
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}r;
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} PAD_VAL;
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typedef union{
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UINT32 GPI;
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struct {
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UINT32 ihbpen:1; // 0 Pad high by pass enable
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UINT32 ihbpinen:1; // 1 Pad high by pass input
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UINT32 instaticen:1; // 2 TBD
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UINT32 ipstaticen:1; // 3 TBD
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UINT32 Overide_strap_pin :1; // 4 DFX indicates if it wants to override the strap pin value on this pad, if exists.
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UINT32 Overide_strap_pin_val:1; // 5 In case DFX need to override strap pin value and it exist for the specific pad, this value will be used.
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UINT32 TestMode_Pin_Mux:3; // 6:9 DFX Pin Muxing
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}r;
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} PAD_DFT;
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//
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// GPIO_USAGE value need to matche the PAD_VAL input/output enable bits.
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//
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typedef enum {
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Native = 0xFF, // Native, no need to set PAD_VALUE
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GPI = 2, // GPI, input only in PAD_VALUE
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GPO = 4, // GPO, output only in PAD_VALUE
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GPIO = 0, // GPIO, input & output
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TRISTS = 6, // Tri-State
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GPIO_NONE
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} GPIO_USAGE;
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typedef enum {
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LO = 0,
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HI = 1,
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NA = 0xFF
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} GPO_D4;
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typedef enum {
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F0 = 0,
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F1 = 1,
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F2 = 2,
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F3 = 3,
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F4 = 4,
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F5 = 5,
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F6 = 6,
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F7 = 7
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} GPIO_FUNC_NUM;
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//
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// Mapping to CONF0 bit 27:24
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// Note: Assume "Direct Irq En" is not set, unless specially notified.
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//
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typedef enum {
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TRIG_ = 0,
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TRIG_Edge_High = /*BIT3 |*/ BIT1, // Positive Edge (Rasing)
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TRIG_Edge_Low = /*BIT3 |*/ BIT2, // Negative Edge (Falling)
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TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1, // Both Edge
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TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0, // Level High
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TRIG_Level_Low = /*BIT3 |*/ BIT2 | BIT0, // Level Low
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} INT_TYPE;
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typedef enum {
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P_20K_H, // Pull Up 20K
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P_20K_L, // Pull Down 20K
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P_10K_H, // Pull Up 10K
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P_10K_L, // Pull Down 10K
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P_2K_H, // Pull Up 2K
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P_2K_L, // Pull Down 2K
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P_NONE // Pull None
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} PULL_TYPE;
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#ifdef EFI_DEBUG
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#define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
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#else
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#define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) { usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
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#endif
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//
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// GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits.
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// NC = NCORE, SC = SCORE, SS= SSUS
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//
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typedef struct {
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#ifdef EFI_DEBUG
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char pad_name[32];// GPIO Pin Name for debug purpose
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#endif
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GPIO_USAGE usage; // GPIO pin used as Native mode or GPI/GPO/GPIO mode
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GPO_D4 gpod4; // GPO default value
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GPIO_FUNC_NUM func; // Function Number (F0~F7)
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INT_TYPE int_type; // Edge or Level trigger, low or high active
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PULL_TYPE pull; // Pull Up or Down
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UINT8 offset; // Equal with (PCONF0 register offset >> 4 bits)
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} GPIO_CONF_PAD_INIT;
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//
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//typedef UINT64 BOARD_FEATURES
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//
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typedef struct _EFI_PLATFORM_INFO_HOB {
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UINT16 PlatformType; // Platform Type
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UINT8 BoardId; // Board ID
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UINT8 BoardRev; // Board Revision
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PLATFORM_FLAVOR PlatformFlavor; // Platform Flavor
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UINT8 DDRDaughterCardCh0Id;// DDR daughter card channel 0 id
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UINT8 DDRDaughterCardCh1Id;// DDR daughter card channel 1 id
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UINT8 ECOId; // ECO applied on platform
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UINT16 IohSku;
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UINT8 IohRevision;
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UINT16 IchSku;
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UINT8 IchRevision;
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EFI_PLATFORM_PCI_DATA PciData;
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EFI_PLATFORM_CPU_DATA CpuData;
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EFI_PLATFORM_MEM_DATA MemData;
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EFI_PLATFORM_SYS_DATA SysData;
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EFI_PLATFORM_IGD_DATA IgdData;
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UINT8 RevisonId; // Structure Revision ID
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EFI_PHYSICAL_ADDRESS PlatformCfioData;
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EFI_PHYSICAL_ADDRESS PlatformGpioData_NC;
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EFI_PHYSICAL_ADDRESS PlatformGpioData_SC;
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EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS;
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EFI_PHYSICAL_ADDRESS PlatformGpioData_NC_TRI;
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EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_TRI;
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EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_TRI;
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EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1;
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EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_PR1_1;
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EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1_1;
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UINT8 CfioEnabled;
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UINT32 SsidSvid;
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UINT16 AudioSubsystemDeviceId;
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UINT64 AcpiOemId;
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UINT64 AcpiOemTableId;
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UINT16 MemCfgID;
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} EFI_PLATFORM_INFO_HOB;
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#pragma pack()
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EFI_STATUS
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GetPlatformInfoHob (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
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);
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EFI_STATUS
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InstallPlatformClocksNotify (
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IN CONST EFI_PEI_SERVICES **PeiServices
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);
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EFI_STATUS
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InstallPlatformSysCtrlGPIONotify (
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IN CONST EFI_PEI_SERVICES **PeiServices
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);
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#endif
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