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ad1db975c0
C code changes for building EDK2 RISC-V platform. Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Co-authored-by: Daniel Helmut Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Bob Feng <bob.c.feng@intel.com> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
338 lines
9.2 KiB
C
338 lines
9.2 KiB
C
/** @file
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IA32 and X64 Specific relocation fixups
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Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
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Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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--*/
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#include <Common/UefiBaseTypes.h>
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#include <IndustryStandard/PeImage.h>
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#include "PeCoffLib.h"
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#include "CommonLib.h"
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#include "EfiUtilityMsgs.h"
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#define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \
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Value |= (((UINT64)((*(Address) >> InstPos) & (((UINT64)1 << Size) - 1))) << ValPos)
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#define INS_IMM64(Value, Address, Size, InstPos, ValPos) \
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*(UINT32*)Address = (*(UINT32*)Address & ~(((1 << Size) - 1) << InstPos)) | \
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((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) << InstPos)
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#define IMM64_IMM7B_INST_WORD_X 3
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#define IMM64_IMM7B_SIZE_X 7
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#define IMM64_IMM7B_INST_WORD_POS_X 4
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#define IMM64_IMM7B_VAL_POS_X 0
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#define IMM64_IMM9D_INST_WORD_X 3
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#define IMM64_IMM9D_SIZE_X 9
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#define IMM64_IMM9D_INST_WORD_POS_X 18
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#define IMM64_IMM9D_VAL_POS_X 7
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#define IMM64_IMM5C_INST_WORD_X 3
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#define IMM64_IMM5C_SIZE_X 5
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#define IMM64_IMM5C_INST_WORD_POS_X 13
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#define IMM64_IMM5C_VAL_POS_X 16
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#define IMM64_IC_INST_WORD_X 3
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#define IMM64_IC_SIZE_X 1
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#define IMM64_IC_INST_WORD_POS_X 12
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#define IMM64_IC_VAL_POS_X 21
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#define IMM64_IMM41a_INST_WORD_X 1
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#define IMM64_IMM41a_SIZE_X 10
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#define IMM64_IMM41a_INST_WORD_POS_X 14
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#define IMM64_IMM41a_VAL_POS_X 22
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#define IMM64_IMM41b_INST_WORD_X 1
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#define IMM64_IMM41b_SIZE_X 8
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#define IMM64_IMM41b_INST_WORD_POS_X 24
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#define IMM64_IMM41b_VAL_POS_X 32
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#define IMM64_IMM41c_INST_WORD_X 2
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#define IMM64_IMM41c_SIZE_X 23
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#define IMM64_IMM41c_INST_WORD_POS_X 0
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#define IMM64_IMM41c_VAL_POS_X 40
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#define IMM64_SIGN_INST_WORD_X 3
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#define IMM64_SIGN_SIZE_X 1
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#define IMM64_SIGN_INST_WORD_POS_X 27
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#define IMM64_SIGN_VAL_POS_X 63
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UINT32 *RiscVHi20Fixup = NULL;
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RETURN_STATUS
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PeCoffLoaderRelocateIa32Image (
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IN UINT16 *Reloc,
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IN OUT CHAR8 *Fixup,
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IN OUT CHAR8 **FixupData,
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IN UINT64 Adjust
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)
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/*++
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Routine Description:
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Performs an IA-32 specific relocation fixup
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Arguments:
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Reloc - Pointer to the relocation record
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Fixup - Pointer to the address to fix up
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FixupData - Pointer to a buffer to log the fixups
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Adjust - The offset to adjust the fixup
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Returns:
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EFI_UNSUPPORTED - Unsupported now
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--*/
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{
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return RETURN_UNSUPPORTED;
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}
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/*++
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Routine Description:
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Performs an RISC-V specific relocation fixup
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Arguments:
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Reloc - Pointer to the relocation record
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Fixup - Pointer to the address to fix up
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FixupData - Pointer to a buffer to log the fixups
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Adjust - The offset to adjust the fixup
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Returns:
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Status code
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--*/
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RETURN_STATUS
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PeCoffLoaderRelocateRiscVImage (
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IN UINT16 *Reloc,
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IN OUT CHAR8 *Fixup,
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IN OUT CHAR8 **FixupData,
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IN UINT64 Adjust
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)
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{
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UINT32 Value;
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UINT32 Value2;
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UINT32 OrgValue;
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OrgValue = *(UINT32 *) Fixup;
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OrgValue = OrgValue;
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switch ((*Reloc) >> 12) {
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case EFI_IMAGE_REL_BASED_RISCV_HI20:
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RiscVHi20Fixup = (UINT32 *) Fixup;
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break;
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case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
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if (RiscVHi20Fixup != NULL) {
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Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
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Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
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if (Value2 & (RISCV_IMM_REACH/2)) {
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Value2 |= ~(RISCV_IMM_REACH-1);
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}
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Value += Value2;
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Value += (UINT32)Adjust;
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Value2 = RISCV_CONST_HIGH_PART (Value);
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*(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
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(RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
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*(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) | \
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(RV_X (*(UINT32 *)Fixup, 0, 20));
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}
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RiscVHi20Fixup = NULL;
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break;
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case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
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if (RiscVHi20Fixup != NULL) {
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Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
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Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5));
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if (Value2 & (RISCV_IMM_REACH/2)) {
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Value2 |= ~(RISCV_IMM_REACH-1);
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}
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Value += Value2;
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Value += (UINT32)Adjust;
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Value2 = RISCV_CONST_HIGH_PART (Value);
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*(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
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(RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
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Value2 = *(UINT32 *)Fixup & 0x01fff07f;
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Value &= RISCV_IMM_REACH - 1;
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*(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
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}
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RiscVHi20Fixup = NULL;
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break;
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default:
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return EFI_UNSUPPORTED;
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}
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return RETURN_SUCCESS;
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}
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/**
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Pass in a pointer to an ARM MOVT or MOVW immediate instruction and
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return the immediate data encoded in the instruction
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@param Instruction Pointer to ARM MOVT or MOVW immediate instruction
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@return Immediate address encoded in the instruction
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**/
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UINT16
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ThumbMovtImmediateAddress (
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IN UINT16 *Instruction
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)
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{
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UINT32 Movt;
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UINT16 Address;
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// Thumb2 is two 16-bit instructions working together. Not a single 32-bit instruction
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// Example MOVT R0, #0 is 0x0000f2c0 or 0xf2c0 0x0000
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Movt = (*Instruction << 16) | (*(Instruction + 1));
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// imm16 = imm4:i:imm3:imm8
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// imm4 -> Bit19:Bit16
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// i -> Bit26
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// imm3 -> Bit14:Bit12
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// imm8 -> Bit7:Bit0
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Address = (UINT16)(Movt & 0x000000ff); // imm8
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Address |= (UINT16)((Movt >> 4) & 0x0000f700); // imm4 imm3
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Address |= (((Movt & BIT26) != 0) ? BIT11 : 0); // i
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return Address;
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}
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/**
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Update an ARM MOVT or MOVW immediate instruction immediate data.
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@param Instruction Pointer to ARM MOVT or MOVW immediate instruction
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@param Address New address to patch into the instruction
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**/
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VOID
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ThumbMovtImmediatePatch (
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IN OUT UINT16 *Instruction,
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IN UINT16 Address
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)
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{
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UINT16 Patch;
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// First 16-bit chunk of instruction
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Patch = ((Address >> 12) & 0x000f); // imm4
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Patch |= (((Address & BIT11) != 0) ? BIT10 : 0); // i
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*Instruction = (*Instruction & ~0x040f) | Patch;
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// Second 16-bit chunk of instruction
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Patch = Address & 0x000000ff; // imm8
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Patch |= ((Address << 4) & 0x00007000); // imm3
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Instruction++;
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*Instruction = (*Instruction & ~0x70ff) | Patch;
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}
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/**
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Pass in a pointer to an ARM MOVW/MOVT instruction pair and
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return the immediate data encoded in the two` instruction
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@param Instructions Pointer to ARM MOVW/MOVT instruction pair
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@return Immediate address encoded in the instructions
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**/
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UINT32
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EFIAPI
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ThumbMovwMovtImmediateAddress (
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IN UINT16 *Instructions
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)
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{
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UINT16 *Word;
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UINT16 *Top;
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Word = Instructions; // MOVW
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Top = Word + 2; // MOVT
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return (ThumbMovtImmediateAddress (Top) << 16) + ThumbMovtImmediateAddress (Word);
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}
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/**
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Update an ARM MOVW/MOVT immediate instruction instruction pair.
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@param Instructions Pointer to ARM MOVW/MOVT instruction pair
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@param Address New address to patch into the instructions
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**/
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VOID
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EFIAPI
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ThumbMovwMovtImmediatePatch (
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IN OUT UINT16 *Instructions,
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IN UINT32 Address
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)
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{
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UINT16 *Word;
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UINT16 *Top;
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Word = (UINT16 *)Instructions; // MOVW
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Top = Word + 2; // MOVT
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ThumbMovtImmediatePatch (Word, (UINT16)(Address & 0xffff));
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ThumbMovtImmediatePatch (Top, (UINT16)(Address >> 16));
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}
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/**
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Performs an ARM-based specific relocation fixup and is a no-op on other
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instruction sets.
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@param Reloc Pointer to the relocation record.
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@param Fixup Pointer to the address to fix up.
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@param FixupData Pointer to a buffer to log the fixups.
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@param Adjust The offset to adjust the fixup.
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@return Status code.
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**/
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RETURN_STATUS
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PeCoffLoaderRelocateArmImage (
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IN UINT16 **Reloc,
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IN OUT CHAR8 *Fixup,
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IN OUT CHAR8 **FixupData,
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IN UINT64 Adjust
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)
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{
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UINT16 *Fixup16;
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UINT32 FixupVal;
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Fixup16 = (UINT16 *) Fixup;
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switch ((**Reloc) >> 12) {
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case EFI_IMAGE_REL_BASED_ARM_MOV32T:
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FixupVal = ThumbMovwMovtImmediateAddress (Fixup16) + (UINT32)Adjust;
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ThumbMovwMovtImmediatePatch (Fixup16, FixupVal);
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if (*FixupData != NULL) {
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*FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
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CopyMem (*FixupData, Fixup16, sizeof (UINT64));
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*FixupData = *FixupData + sizeof(UINT64);
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}
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break;
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case EFI_IMAGE_REL_BASED_ARM_MOV32A:
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// break omitted - ARM instruction encoding not implemented
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default:
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return RETURN_UNSUPPORTED;
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}
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return RETURN_SUCCESS;
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}
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