mirror of https://github.com/acidanthera/audk.git
638 lines
15 KiB
C
638 lines
15 KiB
C
/** @file
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Copyright (c) 2007, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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EhciReg.c
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Abstract:
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The EHCI register operation routines.
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Revision History
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**/
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#include "Ehci.h"
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/**
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Read EHCI capability register
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@param Ehc The Ehc device
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@param Offset Capability register address
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@return The register content read
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**/
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UINT32
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EhcReadCapRegister (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Offset
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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Status = Ehc->PciIo->Mem.Read (
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Ehc->PciIo,
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EfiPciIoWidthUint32,
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EHC_BAR_INDEX,
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(UINT64) Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "EhcReadCapRegister: Pci Io read error - %r at %d\n", Status, Offset));
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Data = 0xFFFF;
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}
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return Data;
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}
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/**
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Read Ehc Operation register
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@param Ehc The EHCI device
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@param Offset The operation register offset
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@return The register content read
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**/
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UINT32
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EhcReadOpReg (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Offset
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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ASSERT (Ehc->CapLen != 0);
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Status = Ehc->PciIo->Mem.Read (
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Ehc->PciIo,
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EfiPciIoWidthUint32,
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EHC_BAR_INDEX,
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(UINT64) (Ehc->CapLen + Offset),
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "EhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
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Data = 0xFFFF;
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}
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return Data;
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}
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/**
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Write the data to the EHCI operation register
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@param Ehc The EHCI device
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@param Offset EHCI operation register offset
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@param Data The data to write
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@return None
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**/
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VOID
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EhcWriteOpReg (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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EFI_STATUS Status;
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ASSERT (Ehc->CapLen != 0);
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Status = Ehc->PciIo->Mem.Write (
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Ehc->PciIo,
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EfiPciIoWidthUint32,
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EHC_BAR_INDEX,
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(UINT64) (Ehc->CapLen + Offset),
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "EhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
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}
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}
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/**
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Set one bit of the operational register while keeping other bits
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@param Ehc The EHCI device
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@param Offset The offset of the operational register
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@param Bit The bit mask of the register to set
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@return None
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**/
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STATIC
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VOID
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EhcSetOpRegBit (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Offset,
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IN UINT32 Bit
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)
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{
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UINT32 Data;
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Data = EhcReadOpReg (Ehc, Offset);
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Data |= Bit;
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EhcWriteOpReg (Ehc, Offset, Data);
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}
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/**
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Clear one bit of the operational register while keeping other bits
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@param Ehc The EHCI device
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@param Offset The offset of the operational register
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@param Bit The bit mask of the register to clear
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@return None
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**/
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STATIC
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VOID
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EhcClearOpRegBit (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Offset,
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IN UINT32 Bit
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)
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{
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UINT32 Data;
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Data = EhcReadOpReg (Ehc, Offset);
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Data &= ~Bit;
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EhcWriteOpReg (Ehc, Offset, Data);
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}
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/**
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Wait the operation register's bit as specified by Bit
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to become set (or clear)
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@param Ehc The EHCI device
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@param Offset The offset of the operation register
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@param Bit The bit of the register to wait for
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@param WaitToSet Wait the bit to set or clear
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@param Timeout The time to wait before abort (in millisecond)
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@retval EFI_SUCCESS The bit successfully changed by host controller
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@retval EFI_TIMEOUT The time out occurred
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**/
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STATIC
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EFI_STATUS
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EhcWaitOpRegBit (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Offset,
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IN UINT32 Bit,
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IN BOOLEAN WaitToSet,
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IN UINT32 Timeout
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)
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{
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UINT32 Index;
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for (Index = 0; Index < Timeout / EHC_SYNC_POLL_INTERVAL + 1; Index++) {
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if (EHC_REG_BIT_IS_SET (Ehc, Offset, Bit) == WaitToSet) {
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return EFI_SUCCESS;
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}
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gBS->Stall (EHC_SYNC_POLL_INTERVAL);
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}
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return EFI_TIMEOUT;
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}
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/**
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Add support for UEFI Over Legacy (UoL) feature, stop
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the legacy USB SMI support
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@param Ehc The EHCI device.
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@return None
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**/
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VOID
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EhcClearLegacySupport (
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IN USB2_HC_DEV *Ehc
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)
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{
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UINT32 ExtendCap;
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EFI_PCI_IO_PROTOCOL *PciIo;
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UINT32 Value;
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UINT32 TimeOut;
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DEBUG ((EFI_D_INFO, "EhcClearLegacySupport: called to clear legacy support\n"));
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PciIo = Ehc->PciIo;
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ExtendCap = (Ehc->HcCapParams >> 8) & 0xFF;
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &Value);
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);
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Value |= (0x1 << 24);
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PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);
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TimeOut = 40;
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while (TimeOut--) {
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gBS->Stall (500);
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);
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if ((Value & 0x01010000) == 0x01000000) {
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break;
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}
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}
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value);
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &Value);
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}
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/**
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Set door bell and wait it to be ACKed by host controller.
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This function is used to synchronize with the hardware.
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@param Ehc The EHCI device
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@param Timeout The time to wait before abort (in millisecond, ms)
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@return EFI_SUCCESS : Synchronized with the hardware
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@return EFI_TIMEOUT : Time out happened while waiting door bell to set
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**/
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EFI_STATUS
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EhcSetAndWaitDoorBell (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Timeout
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)
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{
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EFI_STATUS Status;
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UINT32 Data;
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EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_IAAD);
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Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_IAA, TRUE, Timeout);
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//
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// ACK the IAA bit in USBSTS register. Make sure other
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// interrupt bits are not ACKed. These bits are WC (Write Clean).
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//
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Data = EhcReadOpReg (Ehc, EHC_USBSTS_OFFSET);
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Data &= ~USBSTS_INTACK_MASK;
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Data |= USBSTS_IAA;
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EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, Data);
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return Status;
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}
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/**
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Clear all the interrutp status bits, these bits
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are Write-Clean
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@param Ehc The EHCI device
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@return None
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**/
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VOID
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EhcAckAllInterrupt (
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IN USB2_HC_DEV *Ehc
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)
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{
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EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, USBSTS_INTACK_MASK);
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}
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/**
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Enable the periodic schedule then wait EHC to
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actually enable it.
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@param Ehc The EHCI device
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@param Timeout The time to wait before abort (in millisecond, ms)
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@return EFI_SUCCESS : The periodical schedule is enabled
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@return EFI_TIMEOUT : Time out happened while enabling periodic schedule
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**/
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STATIC
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EFI_STATUS
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EhcEnablePeriodSchd (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Timeout
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)
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{
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EFI_STATUS Status;
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EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);
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Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_PERIOD_ENABLED, TRUE, Timeout);
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return Status;
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}
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/**
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Disable periodic schedule
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@param Ehc The EHCI device
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@param Timeout Time to wait before abort (in millisecond, ms)
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@return EFI_SUCCESS : Periodic schedule is disabled.
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@return EFI_DEVICE_ERROR : Fail to disable periodic schedule
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**/
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EFI_STATUS
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EhcDisablePeriodSchd (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Timeout
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)
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{
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EFI_STATUS Status;
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EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);
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Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_PERIOD_ENABLED, FALSE, Timeout);
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return Status;
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}
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/**
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Enable asynchrounous schedule
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@param Ehc The EHCI device
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@param Timeout Time to wait before abort
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@return EFI_SUCCESS : The EHCI asynchronous schedule is enabled
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@return Others : Failed to enable the asynchronous scheudle
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**/
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STATIC
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EFI_STATUS
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EhcEnableAsyncSchd (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Timeout
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)
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{
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EFI_STATUS Status;
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EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);
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Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_ASYNC_ENABLED, TRUE, Timeout);
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return Status;
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}
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/**
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Disable asynchrounous schedule
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@param Ehc The EHCI device
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@param Timeout Time to wait before abort (in millisecond, ms)
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@return EFI_SUCCESS : The asynchronous schedule is disabled
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@return Others : Failed to disable the asynchronous schedule
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**/
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EFI_STATUS
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EhcDisableAsyncSchd (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Timeout
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)
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{
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EFI_STATUS Status;
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EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);
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Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_ASYNC_ENABLED, FALSE, Timeout);
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return Status;
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}
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/**
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Whether Ehc is halted
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@param Ehc The EHCI device
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@return TRUE : The controller is halted
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@return FALSE : It isn't halted
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**/
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BOOLEAN
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EhcIsHalt (
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IN USB2_HC_DEV *Ehc
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)
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{
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return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT);
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}
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/**
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Whether system error occurred
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@param Ehc The EHCI device
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@return TRUE : System error happened
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@return FALSE : No system error
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**/
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BOOLEAN
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EhcIsSysError (
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IN USB2_HC_DEV *Ehc
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)
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{
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return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_SYS_ERROR);
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}
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/**
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Reset the host controller
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@param Ehc The EHCI device
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@param Timeout Time to wait before abort (in millisecond, ms)
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@return EFI_SUCCESS : The host controller is reset
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@return Others : Failed to reset the host
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**/
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EFI_STATUS
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EhcResetHC (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Timeout
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)
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{
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EFI_STATUS Status;
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//
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// Host can only be reset when it is halt. If not so, halt it
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//
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if (!EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT)) {
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Status = EhcHaltHC (Ehc, Timeout);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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}
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EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RESET);
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Status = EhcWaitOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RESET, FALSE, Timeout);
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return Status;
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}
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/**
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Halt the host controller
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@param Ehc The EHCI device
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@param Timeout Time to wait before abort
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@return EFI_SUCCESS : The EHCI is halt
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@return EFI_TIMEOUT : Failed to halt the controller before Timeout
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**/
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EFI_STATUS
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EhcHaltHC (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Timeout
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)
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{
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EFI_STATUS Status;
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EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
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Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, TRUE, Timeout);
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return Status;
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}
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/**
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Set the EHCI to run
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@param Ehc The EHCI device
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@param Timeout Time to wait before abort
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@return EFI_SUCCESS : The EHCI is running
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@return Others : Failed to set the EHCI to run
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**/
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EFI_STATUS
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EhcRunHC (
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IN USB2_HC_DEV *Ehc,
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IN UINT32 Timeout
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)
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{
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EFI_STATUS Status;
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EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
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Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, FALSE, Timeout);
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return Status;
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}
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/**
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Initialize the HC hardware.
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EHCI spec lists the five things to do to initialize the hardware
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1. Program CTRLDSSEGMENT
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2. Set USBINTR to enable interrupts
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3. Set periodic list base
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4. Set USBCMD, interrupt threshold, frame list size etc
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5. Write 1 to CONFIGFLAG to route all ports to EHCI
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@param Ehc The EHCI device
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@return EFI_SUCCESS : The EHCI has come out of halt state
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@return EFI_TIMEOUT : Time out happened
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**/
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EFI_STATUS
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EhcInitHC (
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IN USB2_HC_DEV *Ehc
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)
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{
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EFI_STATUS Status;
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ASSERT (EhcIsHalt (Ehc));
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//
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// Allocate the periodic frame and associated memeory
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// management facilities if not already done.
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//
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if (Ehc->PeriodFrame != NULL) {
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EhcFreeSched (Ehc);
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}
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Status = EhcInitSched (Ehc);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// 1. Program the CTRLDSSEGMENT register with the high 32 bit addr
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//
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EhcWriteOpReg (Ehc, EHC_CTRLDSSEG_OFFSET, Ehc->High32bitAddr);
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//
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// 2. Clear USBINTR to disable all the interrupt. UEFI works by polling
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//
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EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);
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//
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// 3. Program periodic frame list, already done in EhcInitSched
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// 4. Start the Host Controller
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//
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EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
|
|
|
|
//
|
|
// 5. Set all ports routing to EHC
|
|
//
|
|
EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);
|
|
|
|
//
|
|
// Wait roothub port power stable
|
|
//
|
|
gBS->Stall (EHC_ROOT_PORT_RECOVERY_STALL);
|
|
|
|
Status = EhcEnablePeriodSchd (Ehc, EHC_GENERIC_TIMEOUT);
|
|
|
|
if (EFI_ERROR (Status)) {
|
|
DEBUG ((EFI_D_ERROR, "EhcInitHC: failed to enable period schedule\n"));
|
|
return Status;
|
|
}
|
|
|
|
Status = EhcEnableAsyncSchd (Ehc, EHC_GENERIC_TIMEOUT);
|
|
|
|
if (EFI_ERROR (Status)) {
|
|
DEBUG ((EFI_D_ERROR, "EhcInitHC: failed to enable async schedule\n"));
|
|
return Status;
|
|
}
|
|
|
|
return EFI_SUCCESS;
|
|
}
|