mirror of https://github.com/acidanthera/audk.git
152 lines
4.6 KiB
NASM
152 lines
4.6 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; SmmInit.nasm
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;
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; Abstract:
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;
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; Functions for relocating SMBASE's for all processors
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;
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;-------------------------------------------------------------------------------
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%include "StuffRsbNasm.inc"
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extern ASM_PFX(SmmInitHandler)
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extern ASM_PFX(mRebasedFlag)
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extern ASM_PFX(mSmmRelocationOriginalAddress)
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global ASM_PFX(gPatchSmmInitCr3)
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global ASM_PFX(gPatchSmmInitCr4)
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global ASM_PFX(gPatchSmmInitCr0)
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global ASM_PFX(gPatchSmmInitStack)
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global ASM_PFX(gcSmmInitGdtr)
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global ASM_PFX(gcSmmInitSize)
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global ASM_PFX(gcSmmInitTemplate)
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%define PROTECT_MODE_CS 0x8
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%define PROTECT_MODE_DS 0x20
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SECTION .data
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NullSeg: DQ 0 ; reserved by architecture
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CodeSeg32:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x9b
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DB 0xcf ; LimitHigh
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DB 0 ; BaseHigh
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ProtModeCodeSeg32:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x9b
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DB 0xcf ; LimitHigh
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DB 0 ; BaseHigh
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ProtModeSsSeg32:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x93
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DB 0xcf ; LimitHigh
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DB 0 ; BaseHigh
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DataSeg32:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x93
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DB 0xcf ; LimitHigh
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DB 0 ; BaseHigh
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CodeSeg16:
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DW -1
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DW 0
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DB 0
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DB 0x9b
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DB 0x8f
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DB 0
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DataSeg16:
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DW -1
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DW 0
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DB 0
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DB 0x93
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DB 0x8f
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DB 0
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CodeSeg64:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x9b
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DB 0xaf ; LimitHigh
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DB 0 ; BaseHigh
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GDT_SIZE equ $ - NullSeg
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ASM_PFX(gcSmmInitGdtr):
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DW GDT_SIZE - 1
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DD NullSeg
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SECTION .text
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global ASM_PFX(SmmStartup)
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BITS 16
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ASM_PFX(SmmStartup):
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mov eax, 0x80000001 ; read capability
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cpuid
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mov ebx, edx ; rdmsr will change edx. keep it in ebx.
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and ebx, BIT20 ; extract NX capability bit
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shr ebx, 9 ; shift bit to IA32_EFER.NXE[BIT11] position
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmInitCr3):
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mov cr3, eax
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o32 lgdt [cs:ebp + (ASM_PFX(gcSmmInitGdtr) - ASM_PFX(SmmStartup))]
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmInitCr4):
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mov cr4, eax
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mov ecx, 0xc0000080 ; IA32_EFER MSR
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rdmsr
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or eax, ebx ; set NXE bit if NX is available
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wrmsr
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmInitCr0):
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mov di, PROTECT_MODE_DS
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mov cr0, eax
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jmp PROTECT_MODE_CS : dword @32bit
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BITS 32
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@32bit:
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mov ds, edi
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mov es, edi
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mov fs, edi
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mov gs, edi
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mov ss, edi
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mov esp, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmInitStack):
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call ASM_PFX(SmmInitHandler)
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StuffRsb32
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rsm
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BITS 16
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ASM_PFX(gcSmmInitTemplate):
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mov ebp, ASM_PFX(SmmStartup)
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sub ebp, 0x30000
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jmp ebp
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ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
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BITS 32
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global ASM_PFX(SmmRelocationSemaphoreComplete)
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ASM_PFX(SmmRelocationSemaphoreComplete):
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push eax
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mov eax, [ASM_PFX(mRebasedFlag)]
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mov byte [eax], 1
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pop eax
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jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
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global ASM_PFX(SmmInitFixupAddress)
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ASM_PFX(SmmInitFixupAddress):
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ret
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