mirror of https://github.com/acidanthera/audk.git
71 lines
2.1 KiB
ArmAsm
71 lines
2.1 KiB
ArmAsm
//
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// Copyright (c) 2013-2014, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AsmMacroIoLibV8.h>
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#include <Chipset/AArch64.h>
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#ifndef __clang__
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// Register definitions used by GCC for GICv3 access.
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// These are defined by ARMCC, so keep them in the GCC specific code for now.
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#define ICC_SRE_EL2 S3_4_C12_C9_5
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#define ICC_SRE_EL3 S3_6_C12_C12_5
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#define ICC_CTLR_EL1 S3_0_C12_C12_4
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#define ICC_CTLR_EL3 S3_6_C12_C12_4
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#define ICC_PMR_EL1 S3_0_C4_C6_0
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#endif
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.text
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.align 3
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GCC_ASM_EXPORT(InitializeGicV3)
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/* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */
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ASM_PFX(InitializeGicV3):
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// We have a GICv3. UEFI still uses the GICv2 mode. We must do enough setup
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// to allow Linux to use GICv3 if it chooses.
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// In order to setup NS side we need to enable it first.
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mrs x0, scr_el3
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orr x0, x0, #1
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msr scr_el3, x0
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// Enable SRE at EL3 and ICC_SRE_EL2 access
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mov x0, #((1 << 3) | (1 << 0)) // Enable | SRE
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mrs x1, ICC_SRE_EL3
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orr x1, x1, x0
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msr ICC_SRE_EL3, x1
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isb
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// Enable SRE at EL2 and ICC_SRE_EL1 access..
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mrs x1, ICC_SRE_EL2
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orr x1, x1, x0
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msr ICC_SRE_EL2, x1
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isb
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// Configure CPU interface
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msr ICC_CTLR_EL3, xzr
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isb
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msr ICC_CTLR_EL1, xzr
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isb
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// The MemoryMap view and Register view may not be consistent, So Set PMR again.
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mov w1, #1 << 7 // allow NS access to GICC_PMR
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msr ICC_PMR_EL1, x1
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isb
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// Remove the SCR.NS bit
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mrs x0, scr_el3
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and x0, x0, #~SCR_NS
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msr scr_el3, x0
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ret
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