mirror of https://github.com/acidanthera/audk.git
115 lines
4.5 KiB
C
115 lines
4.5 KiB
C
/** @file
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*
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* Copyright (c) 2011-2016, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __PL011_UART_H__
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#define __PL011_UART_H__
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#define PL011_VARIANT_ZTE 1
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// PL011 Registers
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#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE
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#define UARTDR 0x004
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#define UARTRSR 0x010
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#define UARTECR 0x010
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#define UARTFR 0x014
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#define UARTIBRD 0x024
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#define UARTFBRD 0x028
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#define UARTLCR_H 0x030
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#define UARTCR 0x034
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#define UARTIFLS 0x038
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#define UARTIMSC 0x040
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#define UARTRIS 0x044
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#define UARTMIS 0x048
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#define UARTICR 0x04c
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#define UARTDMACR 0x050
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#else
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#define UARTDR 0x000
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#define UARTRSR 0x004
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#define UARTECR 0x004
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#define UARTFR 0x018
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#define UARTILPR 0x020
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#define UARTIBRD 0x024
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#define UARTFBRD 0x028
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#define UARTLCR_H 0x02C
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#define UARTCR 0x030
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#define UARTIFLS 0x034
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#define UARTIMSC 0x038
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#define UARTRIS 0x03C
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#define UARTMIS 0x040
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#define UARTICR 0x044
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#define UARTDMACR 0x048
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#endif
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#define UARTPID0 0xFE0
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#define UARTPID1 0xFE4
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#define UARTPID2 0xFE8
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#define UARTPID3 0xFEC
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// Data status bits
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#define UART_DATA_ERROR_MASK 0x0F00
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// Status reg bits
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#define UART_STATUS_ERROR_MASK 0x0F
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// Flag reg bits
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#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE
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#define PL011_UARTFR_RI (1 << 0) // Ring indicator
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#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
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#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
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#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
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#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
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#define PL011_UARTFR_BUSY (1 << 8) // UART busy
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#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
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#define PL011_UARTFR_DSR (1 << 3) // Data set ready
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#define PL011_UARTFR_CTS (1 << 1) // Clear to send
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#else
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#define PL011_UARTFR_RI (1 << 8) // Ring indicator
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#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
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#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
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#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
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#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
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#define PL011_UARTFR_BUSY (1 << 3) // UART busy
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#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
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#define PL011_UARTFR_DSR (1 << 1) // Data set ready
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#define PL011_UARTFR_CTS (1 << 0) // Clear to send
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#endif
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// Flag reg bits - alternative names
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#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE
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#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF
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#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF
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#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE
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#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY
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// Control reg bits
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#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
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#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
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#define PL011_UARTCR_RTS (1 << 11) // Request to send
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#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.
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#define PL011_UARTCR_RXE (1 << 9) // Receive enable
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#define PL011_UARTCR_TXE (1 << 8) // Transmit enable
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#define PL011_UARTCR_LBE (1 << 7) // Loopback enable
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#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable
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// Line Control Register Bits
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#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select
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#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
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#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
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#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
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#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
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#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable
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#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select
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#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select
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#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
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#define PL011_UARTLCR_H_BRK (1 << 0) // Send break
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#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)
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#define PL011_VER_R1P4 0x2
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#endif
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