mirror of https://github.com/acidanthera/audk.git
621 lines
15 KiB
NASM
621 lines
15 KiB
NASM
;; @file
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; Provide FSP API entry points.
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;
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; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;;
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.586p
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.model flat,C
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.code
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.xmm
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INCLUDE SaveRestoreSse.inc
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INCLUDE UcodeLoad.inc
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;
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; Following are fixed PCDs
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;
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EXTERN PcdGet32(PcdTemporaryRamBase):DWORD
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EXTERN PcdGet32(PcdTemporaryRamSize):DWORD
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EXTERN PcdGet32(PcdFspTemporaryRamSize):DWORD
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EXTERN PcdGet32(PcdFspAreaSize):DWORD
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;
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; Following functions will be provided in C
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;
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EXTERN SecStartup:PROC
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EXTERN FspApiCallingCheck:PROC
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;
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; Following functions will be provided in PlatformSecLib
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;
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EXTERN GetFspBaseAddress:PROC
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EXTERN GetBootFirmwareVolumeOffset:PROC
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EXTERN Pei2LoaderSwitchStack:PROC
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EXTERN FspSelfCheck(FspSelfCheckDflt):PROC
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EXTERN LoadUcode(LoadUcodeDflt):PROC
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EXTERN SecPlatformInit(SecPlatformInitDflt):PROC
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EXTERN SecCarInit:PROC
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;
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; Define the data length that we saved on the stack top
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;
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DATA_LEN_OF_PER0 EQU 18h
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DATA_LEN_OF_MCUD EQU 18h
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DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)
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;
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; Define SSE macros
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;
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LOAD_MMX_EXT MACRO ReturnAddress, MmxRegister
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mov esi, ReturnAddress
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movd MmxRegister, esi ; save ReturnAddress into MM7
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ENDM
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CALL_MMX_EXT MACRO RoutineLabel, MmxRegister
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local ReturnAddress
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mov esi, offset ReturnAddress
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movd MmxRegister, esi ; save ReturnAddress into MM7
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jmp RoutineLabel
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ReturnAddress:
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ENDM
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RET_ESI_EXT MACRO MmxRegister
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movd esi, MmxRegister ; restore ESP from MM7
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jmp esi
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ENDM
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CALL_MMX MACRO RoutineLabel
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CALL_MMX_EXT RoutineLabel, mm7
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ENDM
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RET_ESI MACRO
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RET_ESI_EXT mm7
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ENDM
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;------------------------------------------------------------------------------
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FspSelfCheckDflt PROC NEAR PUBLIC
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; Inputs:
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; eax -> Return address
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; Outputs:
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; eax -> 0 - Successful, Non-zero - Failed.
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; Register Usage:
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; eax is cleared and ebp is used for return address.
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; All others reserved.
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; Save return address to EBP
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mov ebp, eax
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xor eax, eax
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exit:
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jmp ebp
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FspSelfCheckDflt ENDP
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;------------------------------------------------------------------------------
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SecPlatformInitDflt PROC NEAR PUBLIC
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; Inputs:
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; eax -> Return address
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; Outputs:
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; eax -> 0 - Successful, Non-zero - Failed.
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; Register Usage:
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; eax is cleared and ebp is used for return address.
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; All others reserved.
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; Save return address to EBP
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mov ebp, eax
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xor eax, eax
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exit:
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jmp ebp
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SecPlatformInitDflt ENDP
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;------------------------------------------------------------------------------
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LoadUcodeDflt PROC NEAR PUBLIC
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; Inputs:
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; esp -> LOAD_UCODE_PARAMS pointer
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; Register Usage:
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; esp Preserved
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; All others destroyed
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; Assumptions:
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; No memory available, stack is hard-coded and used for return address
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; Executed by SBSP and NBSP
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; Beginning of microcode update region starts on paragraph boundary
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;
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;
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; Save return address to EBP
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movd ebp, mm7
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cmp esp, 0
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jz paramerror
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mov eax, dword ptr [esp] ; Parameter pointer
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cmp eax, 0
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jz paramerror
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mov esp, eax
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mov esi, [esp].LOAD_UCODE_PARAMS.ucode_code_addr
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cmp esi, 0
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jnz check_main_header
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paramerror:
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mov eax, 080000002h
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jmp exit
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mov esi, [esp].LOAD_UCODE_PARAMS.ucode_code_addr
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check_main_header:
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; Get processor signature and platform ID from the installed processor
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; and save into registers for later use
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; ebx = processor signature
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; edx = platform ID
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mov eax, 1
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cpuid
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mov ebx, eax
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mov ecx, MSR_IA32_PLATFORM_ID
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rdmsr
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mov ecx, edx
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shr ecx, 50-32
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and ecx, 7h
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mov edx, 1
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shl edx, cl
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; Current register usage
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; esp -> stack with paramters
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; esi -> microcode update to check
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; ebx = processor signature
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; edx = platform ID
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; Check for valid microcode header
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; Minimal test checking for header version and loader version as 1
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mov eax, dword ptr 1
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cmp [esi].ucode_hdr.version, eax
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jne advance_fixed_size
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cmp [esi].ucode_hdr.loader, eax
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jne advance_fixed_size
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; Check if signature and plaform ID match
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cmp ebx, [esi].ucode_hdr.processor
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jne @f
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test edx, [esi].ucode_hdr.flags
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jnz load_check ; Jif signature and platform ID match
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@@:
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; Check if extended header exists
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; First check if total_size and data_size are valid
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xor eax, eax
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cmp [esi].ucode_hdr.total_size, eax
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je next_microcode
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cmp [esi].ucode_hdr.data_size, eax
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je next_microcode
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; Then verify total size - sizeof header > data size
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mov ecx, [esi].ucode_hdr.total_size
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sub ecx, sizeof ucode_hdr
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cmp ecx, [esi].ucode_hdr.data_size
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jng next_microcode ; Jif extended header does not exist
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; Set edi -> extended header
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mov edi, esi
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add edi, sizeof ucode_hdr
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add edi, [esi].ucode_hdr.data_size
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; Get count of extended structures
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mov ecx, [edi].ext_sig_hdr.count
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; Move pointer to first signature structure
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add edi, sizeof ext_sig_hdr
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check_ext_sig:
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; Check if extended signature and platform ID match
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cmp [edi].ext_sig.processor, ebx
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jne @f
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test [edi].ext_sig.flags, edx
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jnz load_check ; Jif signature and platform ID match
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@@:
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; Check if any more extended signatures exist
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add edi, sizeof ext_sig
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loop check_ext_sig
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next_microcode:
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; Advance just after end of this microcode
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xor eax, eax
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cmp [esi].ucode_hdr.total_size, eax
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je @f
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add esi, [esi].ucode_hdr.total_size
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jmp check_address
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@@:
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add esi, dword ptr 2048
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jmp check_address
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advance_fixed_size:
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; Advance by 4X dwords
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add esi, dword ptr 1024
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check_address:
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; Is valid Microcode start point ?
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cmp dword ptr [esi].ucode_hdr.version, 0ffffffffh
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jz done
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; Is automatic size detection ?
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mov eax, [esp].LOAD_UCODE_PARAMS.ucode_code_size
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cmp eax, 0ffffffffh
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jz @f
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; Address >= microcode region address + microcode region size?
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add eax, [esp].LOAD_UCODE_PARAMS.ucode_code_addr
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cmp esi, eax
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jae done ;Jif address is outside of ucode region
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jmp check_main_header
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@@:
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load_check:
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; Get the revision of the current microcode update loaded
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mov ecx, MSR_IA32_BIOS_SIGN_ID
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xor eax, eax ; Clear EAX
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xor edx, edx ; Clear EDX
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wrmsr ; Load 0 to MSR at 8Bh
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mov eax, 1
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cpuid
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mov ecx, MSR_IA32_BIOS_SIGN_ID
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rdmsr ; Get current microcode signature
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; Verify this microcode update is not already loaded
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cmp [esi].ucode_hdr.revision, edx
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je continue
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load_microcode:
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; EAX contains the linear address of the start of the Update Data
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; EDX contains zero
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; ECX contains 79h (IA32_BIOS_UPDT_TRIG)
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; Start microcode load with wrmsr
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mov eax, esi
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add eax, sizeof ucode_hdr
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xor edx, edx
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mov ecx, MSR_IA32_BIOS_UPDT_TRIG
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wrmsr
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mov eax, 1
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cpuid
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continue:
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jmp next_microcode
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done:
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mov eax, 1
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cpuid
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mov ecx, MSR_IA32_BIOS_SIGN_ID
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rdmsr ; Get current microcode signature
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xor eax, eax
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cmp edx, 0
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jnz exit
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mov eax, 08000000Eh
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exit:
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jmp ebp
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LoadUcodeDflt ENDP
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EstablishStackFsp PROC NEAR PRIVATE
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;
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; Save parameter pointer in edx
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;
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mov edx, dword ptr [esp + 4]
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;
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; Enable FSP STACK
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;
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mov esp, PcdGet32 (PcdTemporaryRamBase)
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add esp, PcdGet32 (PcdTemporaryRamSize)
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push DATA_LEN_OF_MCUD ; Size of the data region
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push 4455434Dh ; Signature of the data region 'MCUD'
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push dword ptr [edx + 12] ; Code size
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push dword ptr [edx + 8] ; Code base
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cmp edx, 0 ; Is parameter pointer valid ?
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jz InvalidMicrocodeRegion
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push dword ptr [edx + 4] ; Microcode size
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push dword ptr [edx] ; Microcode base
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jmp @F
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InvalidMicrocodeRegion:
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push 0 ; Microcode size
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push 0 ; Microcode base
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@@:
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;
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; Save API entry/exit timestamp into stack
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;
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push DATA_LEN_OF_PER0 ; Size of the data region
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push 30524550h ; Signature of the data region 'PER0'
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LOAD_EDX
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push edx
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LOAD_EAX
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push eax
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rdtsc
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push edx
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push eax
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;
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; Terminator for the data on stack
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;
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push 0
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;
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; Set ECX/EDX to the bootloader temporary memory range
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;
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mov ecx, PcdGet32 (PcdTemporaryRamBase)
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mov edx, ecx
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add edx, PcdGet32 (PcdTemporaryRamSize)
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sub edx, PcdGet32 (PcdFspTemporaryRamSize)
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xor eax, eax
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RET_ESI
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EstablishStackFsp ENDP
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;----------------------------------------------------------------------------
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; TempRamInit API
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;
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; This FSP API will load the microcode update, enable code caching for the
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; region specified by the boot loader and also setup a temporary stack to be
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; used till main memory is initialized.
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;
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;----------------------------------------------------------------------------
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TempRamInitApi PROC NEAR PUBLIC
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;
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; Ensure SSE is enabled
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;
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ENABLE_SSE
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;
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; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6
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;
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SAVE_REGS
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;
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; Save timestamp into XMM4 & XMM5
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;
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rdtsc
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SAVE_EAX
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SAVE_EDX
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;
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; Check Parameter
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;
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mov eax, dword ptr [esp + 4]
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cmp eax, 0
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mov eax, 80000002h
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jz NemInitExit
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;
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; CPUID/DeviceID check
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;
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mov eax, @F
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jmp FspSelfCheck ; Note: ESP can not be changed.
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@@:
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cmp eax, 0
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jnz NemInitExit
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CALL_MMX SecPlatformInit
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cmp eax, 0
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jnz NemInitExit
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; Load microcode
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LOAD_ESP
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CALL_MMX LoadUcode
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cmp eax, 0
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jnz NemInitExit
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; Call Sec CAR Init
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LOAD_ESP
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CALL_MMX SecCarInit
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cmp eax, 0
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jnz NemInitExit
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LOAD_ESP
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CALL_MMX EstablishStackFsp
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NemInitExit:
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;
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; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6
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;
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LOAD_REGS
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ret
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TempRamInitApi ENDP
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;----------------------------------------------------------------------------
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; FspInit API
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;
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; This FSP API will perform the processor and chipset initialization.
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; This API will not return. Instead, it transfers the control to the
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; ContinuationFunc provided in the parameter.
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;
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;----------------------------------------------------------------------------
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FspInitApi PROC NEAR PUBLIC
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mov eax, 1
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jmp FspApiCommon
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FspInitApi ENDP
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;----------------------------------------------------------------------------
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; NotifyPhase API
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;
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; This FSP API will notify the FSP about the different phases in the boot
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; process
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;
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;----------------------------------------------------------------------------
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NotifyPhaseApi PROC C PUBLIC
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mov eax, 2
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jmp FspApiCommon
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NotifyPhaseApi ENDP
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;----------------------------------------------------------------------------
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; FspMemoryInit API
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;
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; This FSP API is called after TempRamInit and initializes the memory.
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;
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;----------------------------------------------------------------------------
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FspMemoryInitApi PROC NEAR PUBLIC
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mov eax, 3
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jmp FspApiCommon
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FspMemoryInitApi ENDP
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;----------------------------------------------------------------------------
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; TempRamExitApi API
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;
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; This API tears down temporary RAM
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;
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;----------------------------------------------------------------------------
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TempRamExitApi PROC C PUBLIC
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mov eax, 4
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jmp FspApiCommon
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TempRamExitApi ENDP
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;----------------------------------------------------------------------------
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; FspSiliconInit API
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;
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; This FSP API initializes the CPU and the chipset including the IO
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; controllers in the chipset to enable normal operation of these devices.
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;
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;----------------------------------------------------------------------------
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FspSiliconInitApi PROC C PUBLIC
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mov eax, 5
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jmp FspApiCommon
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FspSiliconInitApi ENDP
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;----------------------------------------------------------------------------
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; FspApiCommon API
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;
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; This is the FSP API common entry point to resume the FSP execution
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;
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;----------------------------------------------------------------------------
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FspApiCommon PROC C PUBLIC
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;
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; EAX holds the API index
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;
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;
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; Stack must be ready
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;
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push eax
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add esp, 4
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cmp eax, dword ptr [esp - 4]
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jz @F
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mov eax, 080000003h
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jmp exit
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@@:
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;
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; Verify the calling condition
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;
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pushad
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push eax
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call FspApiCallingCheck
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add esp, 4
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cmp eax, 0
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jz @F
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mov dword ptr [esp + 4 * 7], eax
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popad
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ret
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@@:
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popad
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cmp eax, 1 ; FspInit API
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jz @F
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cmp eax, 3 ; FspMemoryInit API
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jz @F
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jmp Pei2LoaderSwitchStack
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@@:
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;
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; FspInit and FspMemoryInit APIs, setup the initial stack frame
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;
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;
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; Store the address in FSP which will return control to the BL
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;
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push offset exit
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;
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; Create a Task Frame in the stack for the Boot Loader
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;
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pushfd ; 2 pushf for 4 byte alignment
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cli
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pushad
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; Reserve 8 bytes for IDT save/restore
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sub esp, 8
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sidt fword ptr [esp]
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;
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; Setup new FSP stack
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;
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mov edi, esp
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mov esp, PcdGet32(PcdTemporaryRamBase)
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add esp, PcdGet32(PcdTemporaryRamSize)
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sub esp, (DATA_LEN_AT_STACK_TOP + 40h)
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;
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; Pass the API Idx to SecStartup
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;
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push eax
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;
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; Pass the bootloader stack to SecStartup
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;
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push edi
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;
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; Pass entry point of the PEI core
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;
|
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call GetFspBaseAddress
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mov edi, eax
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add edi, PcdGet32 (PcdFspAreaSize)
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sub edi, 20h
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add eax, DWORD PTR ds:[edi]
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push eax
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;
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; Pass BFV into the PEI Core
|
|
; It uses relative address to calucate the actual boot FV base
|
|
; For FSP impleantion with single FV, PcdFlashFvRecoveryBase and
|
|
; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
|
|
; they are different. The code below can handle both cases.
|
|
;
|
|
call GetFspBaseAddress
|
|
mov edi, eax
|
|
call GetBootFirmwareVolumeOffset
|
|
add eax, edi
|
|
push eax
|
|
|
|
;
|
|
; Pass stack base and size into the PEI Core
|
|
;
|
|
mov eax, PcdGet32(PcdTemporaryRamBase)
|
|
add eax, PcdGet32(PcdTemporaryRamSize)
|
|
sub eax, PcdGet32(PcdFspTemporaryRamSize)
|
|
push eax
|
|
push PcdGet32(PcdFspTemporaryRamSize)
|
|
|
|
;
|
|
; Pass Control into the PEI Core
|
|
;
|
|
call SecStartup
|
|
|
|
exit:
|
|
ret
|
|
|
|
FspApiCommon ENDP
|
|
|
|
END
|