mirror of https://github.com/acidanthera/audk.git
64 lines
2.6 KiB
C
64 lines
2.6 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Omap3530/Omap3530.h>
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VOID
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ClockInit (
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VOID
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)
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{
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//DPLL1 - DPLL4 are configured part of Configuration header which OMAP3 ROM parses.
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// Enable PLL5 and set to 120 MHz as a reference clock.
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MmioWrite32 (CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));
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MmioWrite32 (CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));
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MmioWrite32 (CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);
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// Turn on functional & interface clocks to the USBHOST power domain
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MmioOr32(CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE
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| CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE);
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MmioOr32(CM_ICLKEN_USBHOST, CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE);
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// Turn on functional & interface clocks to the USBTLL block.
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MmioOr32(CM_FCLKEN3_CORE, CM_FCLKEN3_CORE_EN_USBTLL_ENABLE);
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MmioOr32(CM_ICLKEN3_CORE, CM_ICLKEN3_CORE_EN_USBTLL_ENABLE);
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// Turn on functional & interface clocks to MMC1 and I2C1 modules.
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MmioOr32(CM_FCLKEN1_CORE, CM_FCLKEN1_CORE_EN_MMC1_ENABLE
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| CM_FCLKEN1_CORE_EN_I2C1_ENABLE);
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MmioOr32(CM_ICLKEN1_CORE, CM_ICLKEN1_CORE_EN_MMC1_ENABLE
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| CM_ICLKEN1_CORE_EN_I2C1_ENABLE);
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// Turn on functional & interface clocks to various Peripherals.
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MmioOr32(CM_FCLKEN_PER, CM_FCLKEN_PER_EN_UART3_ENABLE
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| CM_FCLKEN_PER_EN_GPT4_ENABLE
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| CM_FCLKEN_PER_EN_GPIO2_ENABLE
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| CM_FCLKEN_PER_EN_GPIO3_ENABLE
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| CM_FCLKEN_PER_EN_GPIO4_ENABLE
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| CM_FCLKEN_PER_EN_GPIO5_ENABLE
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| CM_FCLKEN_PER_EN_GPIO6_ENABLE);
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MmioOr32(CM_ICLKEN_PER, CM_ICLKEN_PER_EN_UART3_ENABLE
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| CM_ICLKEN_PER_EN_GPT3_ENABLE
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| CM_ICLKEN_PER_EN_GPT4_ENABLE
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| CM_ICLKEN_PER_EN_GPIO2_ENABLE
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| CM_ICLKEN_PER_EN_GPIO3_ENABLE
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| CM_ICLKEN_PER_EN_GPIO4_ENABLE
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| CM_ICLKEN_PER_EN_GPIO5_ENABLE
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| CM_ICLKEN_PER_EN_GPIO6_ENABLE);
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// Turn on functional & inteface clocks to various wakeup modules.
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MmioOr32(CM_FCLKEN_WKUP, CM_FCLKEN_WKUP_EN_GPIO1_ENABLE
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| CM_FCLKEN_WKUP_EN_WDT2_ENABLE);
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MmioOr32(CM_ICLKEN_WKUP, CM_ICLKEN_WKUP_EN_GPIO1_ENABLE
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| CM_ICLKEN_WKUP_EN_WDT2_ENABLE);
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}
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