mirror of https://github.com/acidanthera/audk.git
140 lines
4.4 KiB
C
140 lines
4.4 KiB
C
/** @file
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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IchRegTable.c
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Abstract:
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Register initialization table for Ich.
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--*/
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#include <Library/EfiRegTableLib.h>
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#include "PlatformDxe.h"
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extern EFI_PLATFORM_INFO_HOB mPlatformInfo;
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#define R_EFI_PCI_SVID 0x2C
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EFI_REG_TABLE mSubsystemIdRegs [] = {
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//
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// Program SVID and SID for PCI devices.
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// Combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE in order to boost performance
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//
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PCI_WRITE (
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MC_BUS, MC_DEV, MC_FUN, R_EFI_PCI_SVID, EfiPciWidthUint32,
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V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
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),
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PCI_WRITE (
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IGD_BUS, IGD_DEV, IGD_FUN_0, R_EFI_PCI_SVID, EfiPciWidthUint32,
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V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
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),
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PCI_WRITE(
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DEFAULT_PCI_BUS_NUMBER_PCH, 0, 0, R_EFI_PCI_SVID, EfiPciWidthUint32,
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V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
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),
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PCI_WRITE (
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DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, R_PCH_LPC_SS, EfiPciWidthUint32,
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V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
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),
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PCI_WRITE (
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DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, R_PCH_SATA_SS, EfiPciWidthUint32,
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V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
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),
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PCI_WRITE (
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DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SMBUS, PCI_FUNCTION_NUMBER_PCH_SMBUS, R_PCH_SMBUS_SVID, EfiPciWidthUint32,
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V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
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),
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PCI_WRITE (
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DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_USB, PCI_FUNCTION_NUMBER_PCH_EHCI, R_PCH_EHCI_SVID, EfiPciWidthUint32,
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V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
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),
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PCI_WRITE (
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DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, R_PCH_PCIE_SVID, EfiPciWidthUint32,
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V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
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),
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PCI_WRITE (
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DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, R_PCH_PCIE_SVID, EfiPciWidthUint32,
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V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
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),
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PCI_WRITE (
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DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, R_PCH_PCIE_SVID, EfiPciWidthUint32,
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V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
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),
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PCI_WRITE (
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DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, R_PCH_PCIE_SVID, EfiPciWidthUint32,
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V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
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),
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TERMINATE_TABLE
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};
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/**
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Updates the mSubsystemIdRegs table, and processes it. This should program
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the Subsystem Vendor and Device IDs.
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@retval Returns VOID
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**/
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VOID
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InitializeSubsystemIds (
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)
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{
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EFI_REG_TABLE *RegTablePtr;
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UINT32 SubsystemVidDid;
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SubsystemVidDid = mPlatformInfo.SsidSvid;
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RegTablePtr = mSubsystemIdRegs;
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//
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// While we are not at the end of the table
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//
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while (RegTablePtr->Generic.OpCode != OP_TERMINATE_TABLE) {
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//
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// If the data to write is the original SSID
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//
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if (RegTablePtr->PciWrite.Data ==
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((V_PCH_DEFAULT_SID << 16) |
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V_PCH_INTEL_VENDOR_ID)
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) {
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//
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// Then overwrite it to use the alternate SSID
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//
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RegTablePtr->PciWrite.Data = SubsystemVidDid;
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}
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//
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// Go to next table entry
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//
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RegTablePtr++;
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}
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RegTablePtr = mSubsystemIdRegs;
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//
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// Program the SSVID/SSDID
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//
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ProcessRegTablePci (mSubsystemIdRegs, mPciRootBridgeIo, NULL);
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}
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