mirror of https://github.com/acidanthera/audk.git
132 lines
6.6 KiB
Plaintext
132 lines
6.6 KiB
Plaintext
/** @file
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* Multiple APIC Description Table (MADT)
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*
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* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include "ArmPlatform.h"
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#include <Library/AcpiLib.h>
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#include <Library/ArmLib.h>
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#include <Library/PcdLib.h>
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#include <IndustryStandard/Acpi.h>
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//
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// Multiple APIC Description Table
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//
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#ifdef ARM_JUNO_ACPI_5_0
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#pragma pack (1)
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typedef struct {
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EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
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EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];
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EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
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} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
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#pragma pack ()
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EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
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{
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ARM_ACPI_HEADER (
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EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
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EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
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EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
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),
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//
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// MADT specific fields
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//
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0, // LocalApicAddress
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0, // Flags
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},
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{
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// Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase)
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// Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of
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// ACPI v5.0).
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// On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the
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// Trusted Firmware. When supported, we will need to code to dynamically change the ordering.
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// For now we leave CPU2 (A53-0) at the first position.
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// The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
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// the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase)) // A57-1
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},
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EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)
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};
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#else
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#pragma pack (1)
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typedef struct {
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EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
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EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];
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EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
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EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE MsiFrame;
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} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
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#pragma pack ()
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EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
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{
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ARM_ACPI_HEADER (
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EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
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EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
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EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
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),
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//
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// MADT specific fields
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//
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0, // LocalApicAddress
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0, // Flags
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},
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{
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// Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
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// GsivId, GicRBase, Mpidr)
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// Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
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// ACPI v5.1).
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// On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the
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// Trusted Firmware. When supported, we will need to code to dynamically change the ordering.
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// For now we leave CPU2 (A53-0) at the first position.
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// The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
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// the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
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EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0
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2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
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0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
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EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1
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3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
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0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
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EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2
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4, 2, GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
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0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
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EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3
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5, 3, GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
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0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
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EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0
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0, 4, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
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0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
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EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1
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1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
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0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
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},
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EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0),
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// Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase)
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EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE)
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};
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#endif
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//
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// Reference the table being generated to prevent the optimizer from removing the
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// data structure from the executable
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//
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VOID* CONST ReferenceAcpiTable = &Madt;
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