audk/UefiCpuPkg
Jiaxin Wu a232e0cd2f UefiCpuPkg/PiSmmCpuDxeSmm: Save and restore CR2 only if SmiProfile enable
A page fault (#PF) that triggers an update to the page table only occurs
if SmiProfile is enabled. Therefore, it is necessary to save and restore
the CR2 register if SmiProfile is configured to be enabled.

Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
2024-10-16 04:06:42 +00:00
..
Application/Cpuid
CpuDxe UefiCpuPkg: remove last instances of EFI_D_ 2024-07-31 08:59:21 +00:00
CpuDxeRiscV64 UefiCpuPkg: RiscV64: initialize FPU 2024-10-04 04:53:21 +00:00
CpuFeatures
CpuIo2Dxe
CpuIo2Smm
CpuIoPei
CpuMmio2Dxe
CpuMpPei
CpuS3DataDxe UefiCpuPkg: Save MTRR by lockbox in CpuS3DataDxe 2024-06-04 07:40:27 +00:00
CpuTimerDxeRiscV64
Include UefiCpuPkg: Add SmmCpuPlatformHookBeforeMmiHandler 2024-10-12 08:56:05 +00:00
Library UefiCpuPkg: Add SmmCpuPlatformHookBeforeMmiHandler 2024-10-12 08:56:05 +00:00
MicrocodeMeasurementDxe
PiSmmCommunication
PiSmmCpuDxeSmm UefiCpuPkg/PiSmmCpuDxeSmm: Save and restore CR2 only if SmiProfile enable 2024-10-16 04:06:42 +00:00
ResetVector
SecCore
SecMigrationPei
Test
Universal/Acpi/S3Resume2Pei UefiCpuPkg/S3: Skip CR3 modification in S3Resume for 64-bit PEI 2024-10-10 06:00:56 +00:00
UefiCpuPkg.ci.yaml UefiCpuPkg/UefiCpuPkg.ci.yaml: Add PrEval CI config 2024-09-02 23:20:35 +00:00
UefiCpuPkg.dec UefiCpuPkg: RiscV64: initialize FPU 2024-10-04 04:53:21 +00:00
UefiCpuPkg.dsc UefiCpuPkg: RiscV64: initialize FPU 2024-10-04 04:53:21 +00:00
UefiCpuPkg.uni UefiCpuPkg: Refine the PCD usage comment 2024-06-14 07:02:37 +00:00
UefiCpuPkgExtra.uni