mirror of https://github.com/acidanthera/audk.git
163 lines
6.8 KiB
C
163 lines
6.8 KiB
C
/** @file
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Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.
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Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __PL180_MCI_H
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#define __PL180_MCI_H
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#include <Uefi.h>
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#include <Protocol/MmcHost.h>
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#include <Library/UefiLib.h>
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#include <Library/DebugLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/IoLib.h>
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#include <Library/TimerLib.h>
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#include <Library/PcdLib.h>
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#define PL180_MCI_DXE_VERSION 0x10
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#define MCI_SYSCTL FixedPcdGet32 (PcdPL180MciBaseAddress)
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#define MCI_POWER_CONTROL_REG (MCI_SYSCTL + 0x000)
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#define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL + 0x004)
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#define MCI_ARGUMENT_REG (MCI_SYSCTL + 0x008)
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#define MCI_COMMAND_REG (MCI_SYSCTL + 0x00C)
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#define MCI_RESPCMD_REG (MCI_SYSCTL + 0x010)
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#define MCI_RESPONSE3_REG (MCI_SYSCTL + 0x014)
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#define MCI_RESPONSE2_REG (MCI_SYSCTL + 0x018)
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#define MCI_RESPONSE1_REG (MCI_SYSCTL + 0x01C)
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#define MCI_RESPONSE0_REG (MCI_SYSCTL + 0x020)
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#define MCI_DATA_TIMER_REG (MCI_SYSCTL + 0x024)
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#define MCI_DATA_LENGTH_REG (MCI_SYSCTL + 0x028)
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#define MCI_DATA_CTL_REG (MCI_SYSCTL + 0x02C)
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#define MCI_DATA_COUNTER (MCI_SYSCTL + 0x030)
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#define MCI_STATUS_REG (MCI_SYSCTL + 0x034)
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#define MCI_CLEAR_STATUS_REG (MCI_SYSCTL + 0x038)
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#define MCI_INT0_MASK_REG (MCI_SYSCTL + 0x03C)
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#define MCI_INT1_MASK_REG (MCI_SYSCTL + 0x040)
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#define MCI_SELECT_REG (MCI_SYSCTL + 0x044)
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#define MCI_FIFOCOUNT_REG (MCI_SYSCTL + 0x048)
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#define MCI_FIFO_REG (MCI_SYSCTL + 0x080)
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#define MCI_PERIPH_ID_REG0 (MCI_SYSCTL + 0xFE0)
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#define MCI_PERIPH_ID_REG1 (MCI_SYSCTL + 0xFE4)
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#define MCI_PERIPH_ID_REG2 (MCI_SYSCTL + 0xFE8)
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#define MCI_PERIPH_ID_REG3 (MCI_SYSCTL + 0xFEC)
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#define MCI_PCELL_ID_REG0 (MCI_SYSCTL + 0xFF0)
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#define MCI_PCELL_ID_REG1 (MCI_SYSCTL + 0xFF4)
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#define MCI_PCELL_ID_REG2 (MCI_SYSCTL + 0xFF8)
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#define MCI_PCELL_ID_REG3 (MCI_SYSCTL + 0xFFC)
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#define MCI_PERIPH_ID0 0x80
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#define MCI_PERIPH_ID1 0x11
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#define MCI_PERIPH_ID2 0x04
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#define MCI_PERIPH_ID3 0x00
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#define MCI_PCELL_ID0 0x0D
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#define MCI_PCELL_ID1 0xF0
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#define MCI_PCELL_ID2 0x05
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#define MCI_PCELL_ID3 0xB1
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#define MCI_POWER_OFF 0
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#define MCI_POWER_UP BIT1
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#define MCI_POWER_ON (BIT1 | BIT0)
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#define MCI_POWER_OPENDRAIN BIT6
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#define MCI_POWER_ROD BIT7
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#define MCI_CLOCK_ENABLE BIT8
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#define MCI_CLOCK_POWERSAVE BIT9
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#define MCI_CLOCK_BYPASS BIT10
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#define MCI_CLOCK_WIDEBUS BIT11
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#define MCI_STATUS_CMD_CMDCRCFAIL BIT0
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#define MCI_STATUS_CMD_DATACRCFAIL BIT1
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#define MCI_STATUS_CMD_CMDTIMEOUT BIT2
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#define MCI_STATUS_CMD_DATATIMEOUT BIT3
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#define MCI_STATUS_CMD_TX_UNDERRUN BIT4
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#define MCI_STATUS_CMD_RXOVERRUN BIT5
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#define MCI_STATUS_CMD_RESPEND BIT6
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#define MCI_STATUS_CMD_SENT BIT7
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#define MCI_STATUS_CMD_DATAEND BIT8
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#define MCI_STATUS_CMD_START_BIT_ERROR BIT9
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#define MCI_STATUS_CMD_DATABLOCKEND BIT10
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#define MCI_STATUS_CMD_ACTIVE BIT11
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#define MCI_STATUS_CMD_TXACTIVE BIT12
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#define MCI_STATUS_CMD_RXACTIVE BIT13
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#define MCI_STATUS_CMD_TXFIFOHALFEMPTY BIT14
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#define MCI_STATUS_CMD_RXFIFOHALFFULL BIT15
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#define MCI_STATUS_CMD_TXFIFOFULL BIT16
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#define MCI_STATUS_CMD_RXFIFOFULL BIT17
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#define MCI_STATUS_CMD_TXFIFOEMPTY BIT18
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#define MCI_STATUS_CMD_RXFIFOEMPTY BIT19
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#define MCI_STATUS_CMD_TXDATAAVAILBL BIT20
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#define MCI_STATUS_CMD_RXDATAAVAILBL BIT21
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#define MCI_STATUS_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
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#define MCI_STATUS_RXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
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#define MCI_STATUS_READ_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \
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| MCI_STATUS_CMD_DATATIMEOUT \
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| MCI_STATUS_CMD_RXOVERRUN \
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| MCI_STATUS_CMD_START_BIT_ERROR )
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#define MCI_STATUS_WRITE_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \
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| MCI_STATUS_CMD_DATATIMEOUT \
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| MCI_STATUS_CMD_TX_UNDERRUN )
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#define MCI_STATUS_CMD_ERROR ( MCI_STATUS_CMD_CMDCRCFAIL \
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| MCI_STATUS_CMD_CMDTIMEOUT \
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| MCI_STATUS_CMD_START_BIT_ERROR )
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#define MCI_CLR_CMD_STATUS ( MCI_STATUS_CMD_RESPEND \
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| MCI_STATUS_CMD_SENT \
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| MCI_STATUS_CMD_ERROR )
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#define MCI_CLR_READ_STATUS ( MCI_STATUS_RXDONE \
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| MCI_STATUS_READ_ERROR )
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#define MCI_CLR_WRITE_STATUS ( MCI_STATUS_TXDONE \
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| MCI_STATUS_WRITE_ERROR )
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#define MCI_CLR_ALL_STATUS (BIT11 - 1)
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#define MCI_DATACTL_DISABLE_MASK 0xFE
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#define MCI_DATACTL_ENABLE BIT0
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#define MCI_DATACTL_CONT_TO_CARD 0
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#define MCI_DATACTL_CARD_TO_CONT BIT1
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#define MCI_DATACTL_BLOCK_TRANS 0
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#define MCI_DATACTL_STREAM_TRANS BIT2
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#define MCI_DATACTL_DMA_DISABLED 0
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#define MCI_DATACTL_DMA_ENABLE BIT3
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#define INDX_MASK 0x3F
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#define MCI_CPSM_WAIT_RESPONSE BIT6
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#define MCI_CPSM_LONG_RESPONSE BIT7
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#define MCI_CPSM_LONG_INTERRUPT BIT8
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#define MCI_CPSM_LONG_PENDING BIT9
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#define MCI_CPSM_ENABLE BIT10
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#define MCI_TRACE(txt) DEBUG ((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))
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EFI_STATUS
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EFIAPI
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MciGetDriverName (
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IN EFI_COMPONENT_NAME_PROTOCOL *This,
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IN CHAR8 *Language,
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OUT CHAR16 **DriverName
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);
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EFI_STATUS
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EFIAPI
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MciGetControllerName (
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IN EFI_COMPONENT_NAME_PROTOCOL *This,
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IN EFI_HANDLE ControllerHandle,
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IN EFI_HANDLE ChildHandle OPTIONAL,
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IN CHAR8 *Language,
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OUT CHAR16 **ControllerName
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);
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#endif
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