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All our page tables are allocated from memory whose cacheability attributes are inherited by the cacheability bits in the MMU control register, so there is no need for explicit cache maintenance after updating the page tables. And even if there were, Set/Way operations are not appropriate anyway for ensuring that these changes make it to main memory. So just remove the explicit cache maintenance completely. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18570 6f19259b-4bc3-4df7-8a09-765794883524