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audk/OvmfPkg/RiscVVirt
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Sunil V L 677f2c6f15 OvmfPkg/RiscVVirt: Update README for CLANGDWARF support 
Update the README with instruction to build using CLANGDWARF
toolchain.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Ard Biesheuvel <ardb@kernel.org> # Debian clang version 14.0.6
 		2023-07-31 12:37:12 +00:00
..
Library OvmfPkg/RiscVVirt: Avoid printing hard coded timeout value 2023-07-21 05:56:55 +00:00
PciCpuIo2Dxe OvmfPkg/RiscVVirt: Add PciCpuIo2Dxe module 2023-02-16 05:53:28 +00:00
Sec OvmfPkg/RiscVVirt: SecEntry: Remove unnecessary assembly directives 2023-07-31 12:37:12 +00:00
README.md OvmfPkg/RiscVVirt: Update README for CLANGDWARF support 2023-07-31 12:37:12 +00:00
RiscVVirt.dsc.inc UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode 2023-07-15 14:10:18 +00:00
RiscVVirt.fdf.inc OvmfPkg/RiscVVirt: Add support for separate code and variable store 2023-06-23 04:49:11 +00:00
RiscVVirtQemu.dsc OvmfPkg: move PciEncoding into AcpiPlatformLib 2023-06-23 17:26:37 +00:00
RiscVVirtQemu.fdf OvmfPkg/RiscVVirt: use 'auto' alignment and FIXED for XIP modules 2023-07-31 12:37:12 +00:00
VarStore.fdf.inc OvmfPkg/RiscVVirt: Fix couple of issues in VarStore 2023-06-23 04:49:11 +00:00

README.md

Support for RISC-V QEMU virt platform

Overview

RISC-V QEMU 'virt' is a generic platform which does not correspond to any real hardware.

EDK2 for RISC-V virt platform is a payload (S-mode) for the previous stage M-mode firmware like OpenSBI. It follows PEI less design.

The minimum QEMU version required is 8.1 or with commit 7efd65423a which supports separate pflash devices for EDK2 code and variable storage.

Get edk2 sources

git clone --recurse-submodule git@github.com:tianocore/edk2.git

Build

Using GCC toolchain

Prerequisite: RISC-V GNU compiler toolchain should be installed.

export WORKSPACE=`pwd`
export GCC5_RISCV64_PREFIX=riscv64-linux-gnu-
export PACKAGES_PATH=$WORKSPACE/edk2
export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools
source edk2/edksetup.sh --reconfig
make -C edk2/BaseTools
source edk2/edksetup.sh BaseTools
build -a RISCV64 --buildtarget RELEASE -p OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc -t GCC5

Using CLANGDWARF toolchain (clang + lld)

Prerequisite: LLVM toolchain with clang and lld should be installed.

export WORKSPACE=`pwd`
export CLANGDWARF_BIN=/usr/bin/
export PACKAGES_PATH=$WORKSPACE/edk2
export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools
source edk2/edksetup.sh --reconfig
make -C edk2/BaseTools
source edk2/edksetup.sh BaseTools
build -a RISCV64 --buildtarget RELEASE -p OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc -t CLANGDWARF

After a successful build, two files namely RISCV_VIRT_CODE.fd and RISCV_VIRT_VARS.fd are created.

Test

Below example shows how to boot openSUSE Tumbleweed E20.

  1. RISC-V QEMU pflash devices should be of of size 32MiB.

    truncate -s 32M RISCV_VIRT_CODE.fd

    truncate -s 32M RISCV_VIRT_VARS.fd

  2. Running QEMU

     qemu-system-riscv64 \
 -M virt,pflash0=pflash0,pflash1=pflash1,acpi=off \
 -m 4096 -smp 2 \
 -serial mon:stdio \
 -device virtio-gpu-pci -full-screen \
 -device qemu-xhci \
 -device usb-kbd \
 -device virtio-rng-pci \
 -blockdev node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \
 -blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd \
 -netdev user,id=net0 \
 -device virtio-net-pci,netdev=net0 \
 -device virtio-blk-device,drive=hd0 \
 -drive file=openSUSE-Tumbleweed-RISC-V-E20-efi.riscv64.raw,format=raw,id=hd0