mirror of https://github.com/acidanthera/audk.git
232 lines
7.4 KiB
C
232 lines
7.4 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/IoLib.h>
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#include <Library/ArmTrustZoneLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Drivers/PL341Dmc.h>
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#include <Drivers/PL301Axi.h>
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#include <Drivers/PL310L2Cache.h>
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#include <Library/SerialPortLib.h>
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#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
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// DDR2 timings
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PL341_DMC_CONFIG DDRTimings = {
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.base = ARM_VE_DMC_BASE,
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.phy_ctrl_base = 0x0, //There is no DDR2 PHY controller on CTA9 test chip
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.MaxChip = 1,
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.IsUserCfg = TRUE,
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.User0Cfg = 0x7C924924,
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.User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),
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.HasQos = TRUE,
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.refresh_prd = 0x3D0,
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.cas_latency = 0x8,
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.write_latency = 0x3,
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.t_mrd = 0x2,
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.t_ras = 0xA,
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.t_rc = 0xE,
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.t_rcd = 0x104,
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.t_rfc = 0x2f32,
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.t_rp = 0x14,
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.t_rrd = 0x2,
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.t_wr = 0x4,
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.t_wtr = 0x2,
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.t_xp = 0x2,
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.t_xsr = 0xC8,
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.t_esr = 0x14,
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.MemoryCfg = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |
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DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,
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.MemoryCfg2 = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |
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DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,
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.MemoryCfg3 = 0x00000001,
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.ChipCfg0 = 0x00010000,
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.t_faw = 0x00000A0D,
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.ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4,
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.ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),
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};
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/**
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Return if Trustzone is supported by your platform
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A non-zero value must be returned if you want to support a Secure World on your platform.
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ArmVExpressTrustzoneInit() will later set up the secure regions.
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This function can return 0 even if Trustzone is supported by your processor. In this case,
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the platform will continue to run in Secure World.
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@return A non-zero value if Trustzone supported.
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**/
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UINTN
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ArmPlatformTrustzoneSupported (
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VOID
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)
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{
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return (MmioRead32(ARM_VE_SYS_CFGRW1_REG) & ARM_VE_CFGRW1_TZASC_EN_BIT_MASK);
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}
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/**
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Initialize the Secure peripherals and memory regions
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If Trustzone is supported by your platform then this function makes the required initialization
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of the secure peripherals and memory regions.
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**/
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VOID ArmPlatformTrustzoneInit(VOID) {
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//
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// Setup TZ Protection Controller
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//
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// Set Non Secure access for all devices
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TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_0, 0xFFFFFFFF);
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TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_1, 0xFFFFFFFF);
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TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_2, 0xFFFFFFFF);
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// Remove Non secure access to secure devices
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TZPCClearDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_0,
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ARM_VE_DECPROT_BIT_TZPC | ARM_VE_DECPROT_BIT_DMC_TZASC | ARM_VE_DECPROT_BIT_NMC_TZASC | ARM_VE_DECPROT_BIT_SMC_TZASC);
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TZPCClearDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_2,
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ARM_VE_DECPROT_BIT_EXT_MAST_TZ | ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK | ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK | ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK);
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//
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// Setup TZ Address Space Controller for the SMC. Create 5 Non Secure regions (NOR0, NOR1, SRAM, SMC Peripheral regions)
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//
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// NOR Flash 0 non secure (BootMon)
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TZASCSetRegion(ARM_VE_TZASC_BASE,1,TZASC_REGION_ENABLED,
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ARM_VE_SMB_NOR0_BASE,0,
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TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);
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// NOR Flash 1. The first half of the NOR Flash1 must be secure for the secure firmware (sec_uefi.bin)
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#if EDK2_ARMVE_SECURE_SYSTEM
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//Note: Your OS Kernel must be aware of the secure regions before to enable this region
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TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,
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ARM_VE_SMB_NOR1_BASE + SIZE_32MB,0,
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TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW);
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#else
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TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,
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ARM_VE_SMB_NOR1_BASE,0,
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TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);
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#endif
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// Base of SRAM. Only half of SRAM in Non Secure world
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// First half non secure (16MB) + Second Half secure (16MB) = 32MB of SRAM
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#if EDK2_ARMVE_SECURE_SYSTEM
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//Note: Your OS Kernel must be aware of the secure regions before to enable this region
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TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,
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ARM_VE_SMB_SRAM_BASE,0,
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TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW);
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#else
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TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,
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ARM_VE_SMB_SRAM_BASE,0,
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TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW);
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#endif
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// Memory Mapped Peripherals. All in non secure world
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TZASCSetRegion(ARM_VE_TZASC_BASE,4,TZASC_REGION_ENABLED,
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ARM_VE_SMB_PERIPH_BASE,0,
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TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);
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// MotherBoard Peripherals and On-chip peripherals.
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TZASCSetRegion(ARM_VE_TZASC_BASE,5,TZASC_REGION_ENABLED,
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ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE,0,
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TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW);
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}
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/**
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Return the current Boot Mode
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This function returns the boot reason on the platform
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@return Return the current Boot Mode of the platform
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**/
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EFI_BOOT_MODE
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ArmPlatformGetBootMode (
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VOID
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)
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{
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return BOOT_WITH_FULL_CONFIGURATION;
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}
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/**
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Remap the memory at 0x0
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Some platform requires or gives the ability to remap the memory at the address 0x0.
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This function can do nothing if this feature is not relevant to your platform.
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**/
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VOID
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ArmPlatformBootRemapping (
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VOID
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)
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{
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UINT32 val32 = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
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// we remap the DRAM to 0x0
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MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (val32 & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
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}
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/**
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Initialize controllers that must setup at the early stage
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Some peripherals must be initialized in Secure World.
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For example, some L2x0 requires to be initialized in Secure World
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**/
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VOID
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ArmPlatformSecInitialize (
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VOID
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) {
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// The L2x0 controller must be intialize in Secure World
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L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase),
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PL310_TAG_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
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PL310_DATA_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
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0,~0, // Use default setting for the Auxiliary Control Register
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FALSE);
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}
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/**
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Initialize controllers that must setup in the normal world
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This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
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in the PEI phase.
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**/
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VOID
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ArmPlatformNormalInitialize (
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VOID
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)
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{
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// Nothing to do here
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}
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/**
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Initialize the system (or sometimes called permanent) memory
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This memory is generally represented by the DRAM.
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**/
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VOID
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ArmPlatformInitializeSystemMemory (
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VOID
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)
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{
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PL341DmcInit(&DDRTimings);
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PL301AxiInit(ARM_VE_FAXI_BASE);
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}
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