mirror of https://github.com/acidanthera/audk.git
693 lines
28 KiB
C
693 lines
28 KiB
C
/*++
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Module Name:
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Configuration.h
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Abstract:
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Driver configuration include file
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--*/
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#ifndef _CONFIGURATION_H
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#define _CONFIGURATION_H
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#define EFI_NON_DEVICE_CLASS 0x00
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#define EFI_DISK_DEVICE_CLASS 0x01
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#define EFI_VIDEO_DEVICE_CLASS 0x02
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#define EFI_NETWORK_DEVICE_CLASS 0x04
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#define EFI_INPUT_DEVICE_CLASS 0x08
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#define EFI_ON_BOARD_DEVICE_CLASS 0x10
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#define EFI_OTHER_DEVICE_CLASS 0x20
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//
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// Processor labels
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//
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#define PROCESSOR_HT_MODE 0x0100
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#define PROCESSOR_FSB_MULTIPLIER 0x0101
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#define PROCESSOR_MULTIPLIER_OVERRIDE_CONTROL 0x0211
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//
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// Memory labels
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//
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#define MEMORY_SLOT1_SPEED 0x0200
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#define MEMORY_SLOT2_SPEED 0x0201
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#define MEMORY_SLOT3_SPEED 0x0202
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#define MEMORY_SLOT4_SPEED 0x0203
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#define END_MEMORY_SLOT_SPEED 0x020F
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#define PERFORMANCE_MEMORY_PROFILE_CONTROL 0x0210
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#define UCLK_RATIO_CONTROL 0x0212
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//
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// Language label
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//
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#define FRONT_PAGE_ITEM_LANGUAGE 0x300
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//
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// Boot Labels
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//
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#define BOOT_DEVICE_PRIORITY_BEGIN 0x0400
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#define BOOT_DEVICE_PRIORITY_END 0x0401
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#define BOOT_OPTICAL_DEVICE_BEGIN 0x0410
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#define BOOT_OPTICAL_DEVICE_END 0x0411
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#define BOOT_REMOVABLE_DEVICE_BEGIN 0x0420
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#define BOOT_REMOVABLE_DEVICE_END 0x0421
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#define BOOT_PXE_DEVICE_BEGIN 0x0430
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#define BOOT_PXE_DEVICE_END 0x0431
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#define BOOT_MENU_TYPE_BEGIN 0x0440
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#define BOOT_MENU_TYPE_END 0x0441
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#define BOOT_USB_DEVICE_BEGIN 0x0450
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#define BOOT_USB_DEVICE_END 0x0451
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#define BOOT_USB_FIRST_BEGIN 0x0460
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#define BOOT_USB_FIRST_END 0x0461
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#define BOOT_UEFI_BEGIN 0x0470
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#define BOOT_UEFI_END 0x0471
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#define BOOT_USB_UNAVAILABLE_BEGIN 0x0480
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#define BOOT_USB_UNAVAILABLE_END 0x0481
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#define BOOT_CD_UNAVAILABLE_BEGIN 0x0490
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#define BOOT_CD_UNAVAILABLE_END 0x0491
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#define BOOT_FDD_UNAVAILABLE_BEGIN 0x04A0
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#define BOOT_FDD_UNAVAILABLE_END 0x04A1
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#define BOOT_DEVICE_PRIORITY_DEFAULT_BEGIN 0x04B0
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#define BOOT_DEVICE_PRIORITY_DEFAULT_END 0x04B1
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#define BOOT_USB_OPT_LABEL_BEGIN 0x04C0
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#define BOOT_USB_OPT_LABEL_END 0x04C1
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#define VAR_EQ_ADMIN_NAME 0x0041 // A
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#define VAR_EQ_ADMIN_DECIMAL_NAME L"65"
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#define VAR_EQ_VIEW_ONLY_NAME 0x0042 // B
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#define VAR_EQ_VIEW_ONLY_DECIMAL_NAME L"66"
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#define VAR_EQ_CONFIG_MODE_NAME 0x0043 // C
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#define VAR_EQ_CONFIG_MODE_DECIMAL_NAME L"67"
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#define VAR_EQ_CPU_EE_NAME 0x0045 // E
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#define VAR_EQ_CPU_EE_DECIMAL_NAME L"69"
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#define VAR_EQ_FLOPPY_MODE_NAME 0x0046 // F
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#define VAR_EQ_FLOPPY_MODE_DECIMAL_NAME L"70"
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#define VAR_EQ_HT_MODE_NAME 0x0048 // H
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#define VAR_EQ_HT_MODE_DECIMAL_NAME L"72"
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#define VAR_EQ_AHCI_MODE_NAME 0x0049 // I
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#define VAR_EQ_AHCI_MODE_DECIMAL_NAME L"73"
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#define VAR_EQ_CPU_LOCK_NAME 0x004C // L
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#define VAR_EQ_CPU_LOCK_DECIMAL_NAME L"76"
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#define VAR_EQ_NX_MODE_NAME 0x004E // N
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#define VAR_EQ_NX_MODE_DECIMAL_NAME L"78"
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#define VAR_EQ_RAID_MODE_NAME 0x0052 // R
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#define VAR_EQ_RAID_MODE_DECIMAL_NAME L"82"
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#define VAR_EQ_1394_MODE_NAME 0x0054 // T
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#define VAR_EQ_1394_MODE_DECIMAL_NAME L"84"
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#define VAR_EQ_USER_NAME 0x0055 // U
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#define VAR_EQ_USER_DECIMAL_NAME L"85"
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#define VAR_EQ_VIDEO_MODE_NAME 0x0056 // V
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#define VAR_EQ_VIDEO_MODE_DECIMAL_NAME L"86"
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#define VAR_EQ_LEGACY_FP_AUDIO_NAME 0x0057 // W
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#define VAR_EQ_LEGACY_FP_AUDIO_DECIMAL_NAME L"87"
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#define VAR_EQ_EM64T_CAPABLE_NAME 0x0058 // X
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#define VAR_EQ_EM64T_CAPABLE_DECIMAL_NAME L"88"
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#define VAR_EQ_BOARD_FORMFACTOR_NAME 0x0059 // Y
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#define VAR_EQ_BOARD_FORMFACTOR_DECIMAL_NAME L"89"
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#define VAR_EQ_UNCON_CPU_NAME 0x005B // ??
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#define VAR_EQ_UNCON_CPU_DECIMAL_NAME L"91"
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#define VAR_EQ_VAR_HIDE_NAME 0x005C // ??
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#define VAR_EQ_VAR_HIDE_DECIMAL_NAME L"92"
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#define VAR_EQ_ENERGY_LAKE_NAME 0x005D // ??
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#define VAR_EQ_ENERGY_LAKE_DECIMAL_NAME L"93"
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#define VAR_EQ_TPM_MODE_NAME 0x005E // ^
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#define VAR_EQ_TPM_MODE_DECIMAL_NAME L"94"
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#define VAR_EQ_DISCRETE_SATA_NAME 0x005F // ??
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#define VAR_EQ_DISCRETE_SATA_DECIMAL_NAME L"95"
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#define VAR_EQ_ROEM_SKU_NAME 0x0060 // ??
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#define VAR_EQ_ROEM_SKU_DECIMAL_NAME L"96"
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#define VAR_EQ_AMTSOL_MODE_NAME 0x0061 // ??
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#define VAR_EQ_AMTSOL_MODE_DECIMAL_NAME L"97"
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#define VAR_EQ_NO_PEG_MODE_NAME 0x0062 // ??
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#define VAR_EQ_NO_PEG_MODE_DECIMAL_NAME L"98"
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#define VAR_EQ_SINGLE_PROCESSOR_MODE_NAME 0x0063 // ??
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#define VAR_EQ_SINGLE_PROCESSOR_MODE_DECIMAL_NAME L"99"
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#define VAR_EQ_FLOPPY_HIDE_NAME 0x0064 // ??
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#define VAR_EQ_FLOPPY_HIDE_DECIMAL_NAME L"100"
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#define VAR_EQ_SERIAL_HIDE_NAME 0x0065 // ??
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#define VAR_EQ_SERIAL_HIDE_DECIMAL_NAME L"101"
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#define VAR_EQ_GV3_CAPABLE_NAME 0x0066 // f
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#define VAR_EQ_GV3_CAPABLE_DECIMAL_NAME L"102"
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#define VAR_EQ_2_MEMORY_NAME 0x0067 // ??
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#define VAR_EQ_2_MEMORY_DECIMAL_NAME L"103"
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#define VAR_EQ_2_SATA_NAME 0x0068 // ??
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#define VAR_EQ_2_SATA_DECIMAL_NAME L"104"
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#define VAR_EQ_NEC_SKU_NAME 0x0069 // ??
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#define VAR_EQ_NEC_SKU_DECIMAL_NAME L"105"
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#define VAR_EQ_AMT_MODE_NAME 0x006A // ??
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#define VAR_EQ_AMT_MODE_DECIMAL_NAME L"106"
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#define VAR_EQ_LCLX_SKU_NAME 0x006B // ??
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#define VAR_EQ_LCLX_SKU_DECIMAL_NAME L"107"
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#define VAR_EQ_VT_NAME 0x006C
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#define VAR_EQ_VT_DECIMAL_NAME L"108"
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#define VAR_EQ_LT_NAME 0x006D
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#define VAR_EQ_LT_DECIMAL_NAME L"109"
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#define VAR_EQ_ITK_BIOS_MOD_NAME 0x006E // ??
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#define VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME L"110"
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#define VAR_EQ_HPET_NAME 0x006F
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#define VAR_EQ_HPET_DECIMAL_NAME L"111"
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#define VAR_EQ_ADMIN_INSTALLED_NAME 0x0070 // ??
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#define VAR_EQ_ADMIN_INSTALLED_DECIMAL_NAME L"112"
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#define VAR_EQ_USER_INSTALLED_NAME 0x0071 // ??
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#define VAR_EQ_USER_INSTALLED_DECIMAL_NAME L"113"
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#define VAR_EQ_CPU_CMP_NAME 0x0072
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#define VAR_EQ_CPU_CMP_DECIMAL_NAME L"114"
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#define VAR_EQ_LAN_MAC_ADDR_NAME 0x0073 // ??
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#define VAR_EQ_LAN_MAC_ADDR_DECIMAL_NAME L"115"
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#define VAR_EQ_PARALLEL_HIDE_NAME 0x0074 // ??
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#define VAR_EQ_PARALLEL_HIDE_DECIMAL_NAME L"116"
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#define VAR_EQ_AFSC_SETUP_NAME 0x0075
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#define VAR_EQ_AFSC_SETUP_DECIMAL_NAME L"117"
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#define VAR_EQ_MINICARD_MODE_NAME 0x0076 //
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#define VAR_EQ_MINICARD_MODE_DECIMAL_NAME L"118"
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#define VAR_EQ_VIDEO_IGD_NAME 0x0077 //
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#define VAR_EQ_VIDEO_IGD_DECIMAL_NAME L"119"
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#define VAR_EQ_ALWAYS_ENABLE_LAN_NAME 0x0078 //
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#define VAR_EQ_ALWAYS_ENABLE_LAN_DECIMAL_NAME L"120"
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#define VAR_EQ_LEGACY_FREE_NAME 0x0079 //
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#define VAR_EQ_LEGACY_FREE_DECIMAL_NAME L"121"
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#define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_NAME 0x007A
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#define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_DECIMAL_NAME L"122"
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#define VAR_EQ_CPU_FSB_NAME 0x007B //
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#define VAR_EQ_CPU_FSB_DECIMAL_NAME L"123"
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#define VAR_EQ_SATA0_DEVICE_NAME 0x007C //
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#define VAR_EQ_SATA0_DVICE_DECIMAL_NAME L"124"
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#define VAR_EQ_SATA1_DEVICE_NAME 0x007D //
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#define VAR_EQ_SATA1_DVICE_DECIMAL_NAME L"125"
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#define VAR_EQ_SATA2_DEVICE_NAME 0x007E //
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#define VAR_EQ_SATA2_DVICE_DECIMAL_NAME L"126"
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#define VAR_EQ_SATA3_DEVICE_NAME 0x007F //
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#define VAR_EQ_SATA3_DVICE_DECIMAL_NAME L"127"
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#define VAR_EQ_SATA4_DEVICE_NAME 0x0080 //
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#define VAR_EQ_SATA4_DVICE_DECIMAL_NAME L"128"
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#define VAR_EQ_SATA5_DEVICE_NAME 0x0081 //
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#define VAR_EQ_SATA5_DVICE_DECIMAL_NAME L"129"
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#define VAR_EQ_TPM_STATUS_NAME 0x0082 // To indicate if TPM is enabled
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#define VAR_EQ_TPM_STATUS_DECIMAL_NAME L"130"
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#define VAR_EQ_HECETA6E_PECI_CPU_NAME 0x0083
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#define VAR_EQ_HECETA6E_PECI_CPU_DECIMAL_NAME L"131"
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#define VAR_EQ_USB_2_NAME 0x0084 //
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#define VAR_EQ_USB_2_DECIMAL_NAME L"132"
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#define VAR_EQ_RVP_NAME 0x0085 //
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#define VAR_EQ_RVP_DECIMAL_NAME L"133"
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#define VAR_EQ_ECIR_NAME 0x0086
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#define VAR_EQ_ECIR_DECIMAL_NAME L"134"
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#define VAR_EQ_WAKONS5KB_NAME 0x0087
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#define VAR_EQ_WAKONS5KB_DECIMAL_NAME L"135"
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#define VAR_EQ_HDAUDIOLINKBP_NAME 0x0088
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#define VAR_EQ_HDAUDIOLINKBP_DECIMAL_NAME L"136"
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#define VAR_EQ_FINGERPRINT_NAME 0x0089
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#define VAR_EQ_FINGERPRINT_DECIMAL_NAME L"137"
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#define VAR_EQ_BLUETOOTH_NAME 0x008A
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#define VAR_EQ_BLUETOOTH_DECIMAL_NAME L"138"
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#define VAR_EQ_WLAN_NAME 0x008B
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#define VAR_EQ_WLAN_DECIMAL_NAME L"139"
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#define VAR_EQ_1_PATA_NAME 0x008C
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#define VAR_EQ_1_PATA_DECIMAL_NAME L"140"
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#define VAR_EQ_ACTIVE_PROCESSOR_CORE_NAME 0x008D
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#define VAR_EQ_ACTIVE_PROCESSOR_CORE_DECIMAL_NAME L"141"
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#define VAR_EQ_TURBO_MODE_CAP_NAME 0x008E
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#define VAR_EQ_TURBO_MODE_CAP_DECIMAL_NAME L"142"
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#define VAR_EQ_XE_MODE_CAP_NAME 0x008F
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#define VAR_EQ_XE_MODE_CAP_DECIMAL_NAME L"143"
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#define VAR_EQ_NPI_QPI_VOLTAGE_NAME 0x0090
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#define VAR_EQ_NPI_QPI_VOLTAGE_DECIMAL_NAME L"144"
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#define VAR_EQ_PRE_PROD_NON_XE_NAME 0x0091
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#define VAR_EQ_PRE_PROD_NON_XE_DECIMAL_NAME L"145"
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#define VAR_EQ_2_C0_MEMORY_NAME 0x0092 // ??
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#define VAR_EQ_2_C0_MEMORY_DECIMAL_NAME L"146"
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#define VAR_EQ_LVDS_NAME 0x0093
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#define VAR_EQ_LVDS_DECIMAL_NAME L"147"
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#define VAR_EQ_USB_OPTION_SHOW_NAME 0x0094
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#define VAR_EQ_USB_OPTION_SHOW_DECIMAL_NAME L"148"
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#define VAR_EQ_HDD_MASTER_INSTALLED_NAME 0x0095
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#define VAR_EQ_HDD_MASTER_INSTALLED_DECIMAL_NAME L"149"
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#define VAR_EQ_HDD_USER_INSTALLED_NAME 0x0096
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#define VAR_EQ_HDD_USER_INSTALLED_DECIMAL_NAME L"150"
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#define VAR_EQ_PS2_HIDE_NAME 0x0097 // ??
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#define VAR_EQ_PS2_HIDE_DECIMAL_NAME L"151"
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#define VAR_EQ_VIDEO_SLOT_NAME 0x0098
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#define VAR_EQ_VIDEO_SLOT_DECIMAL_NAME L"152"
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#define VAR_EQ_HDMI_SLOT_NAME 0x0099
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#define VAR_EQ_HDMI_SLOT_DECIMAL_NAME L"153"
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#define VAR_EQ_SERIAL2_HIDE_NAME 0x009a
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#define VAR_EQ_SERIAL2_HIDE_DECIMAL_NAME L"154"
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#define VAR_EQ_LVDS_WARNING_HIDE_NAME 0x009e
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#define VAR_EQ_LVDS_WARNING_HIDE_DECIMAL_NAME L"158"
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#define VAR_EQ_MSATA_HIDE_NAME 0x009f
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#define VAR_EQ_MSATA_HIDE_DECIMAL_NAME L"159"
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#define VAR_EQ_PCI_SLOT1_NAME 0x00a0
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#define VAR_EQ_PCI_SLOT1_DECIMAL_NAME L"160"
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#define VAR_EQ_PCI_SLOT2_NAME 0x00a1
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#define VAR_EQ_PCI_SLOT2_DECIMAL_NAME L"161"
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//
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// Generic Form Ids
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//
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#define ROOT_FORM_ID 1
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//
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// Advance Page. Do not have to be sequential but have to be unique
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//
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#define CONFIGURATION_ROOT_FORM_ID 2
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#define BOOT_CONFIGURATION_ID 3
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#define ONBOARDDEVICE_CONFIGURATION_ID 4
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#define DRIVE_CONFIGURATION_ID 5
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#define FLOPPY_CONFIGURATION_ID 6
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#define EVENT_LOG_CONFIGURATION_ID 7
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#define VIDEO_CONFIGURATION_ID 8
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#define USB_CONFIGURATION_ID 9
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#define HARDWARE_MONITOR_CONFIGURATION_ID 10
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#define VIEW_EVENT_LOG_CONFIGURATION_ID 11
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#define MEMORY_OVERRIDE_ID 12
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#define CHIPSET_CONFIGURATION_ID 13
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#define BURN_IN_MODE_ID 14
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#define PCI_EXPRESS_ID 15
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#define MANAGEMENT_CONFIGURATION_ID 16
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#define CPU_CONFIGURATION_ID 17
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#define PCI_CONFIGURATION_ID 18
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#define SECURITY_CONFIGURATION_ID 19
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#define ZIP_CONFIGURATION_ID 20
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#define AFSC_FAN_CONTROL_ID 21
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#define VFR_FORMID_CSI 22
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#define VFR_FORMID_MEMORY 23
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#define VFR_FORMID_IOH 24
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#define VFR_FORMID_CPU_CSI 25
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#define VFR_FORMID_IOH_CONFIG 26
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#define VFR_FORMID_VTD 27
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#define VFR_FORMID_PCIE_P0 28
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#define VFR_FORMID_PCIE_P1 29
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#define VFR_FORMID_PCIE_P2 30
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#define VFR_FORMID_PCIE_P3 31
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#define VFR_FORMID_PCIE_P4 32
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#define VFR_FORMID_PCIE_P5 33
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#define VFR_FORMID_PCIE_P6 34
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#define VFR_FORMID_PCIE_P7 35
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#define VFR_FORMID_PCIE_P8 36
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#define VFR_FORMID_PCIE_P9 37
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#define VFR_FORMID_PCIE_P10 38
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#define VFR_FID_SKT0 39
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#define VFR_FID_IOH0 40
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#define VFR_FID_IOH_DEV_HIDE 41
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#define PROCESSOR_OVERRIDES_FORM_ID 42
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#define BUS_OVERRIDES_FORM_ID 43
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#define REF_OVERRIDES_FORM_ID 44
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#define MEMORY_INFORMATION_ID 45
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#define LVDS_WARNING_ID 46
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#define LVDS_CONFIGURATION_ID 47
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#define PCI_SLOT_CONFIGURATION_ID 48
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#define HECETA_CONFIGURATION_ID 49
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#define LVDS_EXPERT_CONFIGURATION_ID 50
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#define PCI_SLOT_7_ID 51
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#define PCI_SLOT_6_ID 52
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#define PCI_SLOT_5_ID 53
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#define PCI_SLOT_4_ID 54
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#define PCI_SLOT_3_ID 55
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#define PCI_SLOT_2_ID 56
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#define PCI_SLOT_1_ID 57
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#define BOOT_DISPLAY_ID 58
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#define CPU_PWR_CONFIGURATION_ID 59
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#define FSC_CONFIGURATION_ID 60
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#define FSC_CPU_TEMPERATURE_FORM_ID 61
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#define FSC_VTT_VOLTAGE_FORM_ID 62
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#define FSC_FEATURES_CONTROL_ID 63
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#define FSC_FAN_CONFIGURATION_ID 64
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#define FSC_PROCESSOR_FAN_CONFIGURATION_ID 65
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#define FSC_FRONT_FAN_CONFIGURATION_ID 66
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#define FSC_REAR_FAN_CONFIGURATION_ID 67
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#define FSC_AUX_FAN_CONFIGURATION_ID 68
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#define FSC_12_VOLTAGE_FORM_ID 69
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#define FSC_5_VOLTAGE_FORM_ID 70
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#define FSC_3P3_VOLTAGE_FORM_ID 71
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#define FSC_2P5_VOLTAGE_FORM_ID 72
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#define FSC_VCC_VOLTAGE_FORM_ID 73
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#define FSC_PCH_TEMPERATURE_FORM_ID 74
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#define FSC_MEM_TEMPERATURE_FORM_ID 75
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#define FSC_VR_TEMPERATURE_FORM_ID 76
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#define FSC_3P3STANDBY_VOLTAGE_FORM_ID 77
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#define FSC_5BACKUP_VOLTAGE_FORM_ID 78
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#define ROOT_MAIN_FORM_ID 79
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#define ROOT_BOOT_FORM_ID 80
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#define ROOT_MAINTENANCE_ID 81
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#define ROOT_POWER_FORM_ID 82
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#define ROOT_SECURITY_FORM_ID 83
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#define ROOT_PERFORMANCE_FORM_ID 84
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#define ROOT_SYSTEM_SETUP_FORM_ID 85
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#define ADDITIONAL_SYSTEM_INFO_FORM_ID 86
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#define THERMAL_CONFIG_FORM_ID 87
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#define PCI_SLOT_CONFIG_LABEL_ID_1 0x300A
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#define PCI_SLOT_CONFIG_LABEL_ID_2 0x300B
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#define PCI_SLOT_CONFIG_LABEL_ID_3 0x300C
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#define PCI_SLOT_CONFIG_LABEL_ID_4 0x300D
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#define PCI_SLOT_CONFIG_LABEL_ID_5 0x300E
|
|
#define PCI_SLOT_CONFIG_LABEL_ID_6 0x300F
|
|
#define PCI_SLOT_CONFIG_LABEL_ID_7 0x3010
|
|
#define PCI_SLOT_CONFIG_LABEL_ID_8 0x3011
|
|
|
|
//
|
|
// Advance Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique
|
|
//
|
|
#define CONFIGURATION_HARDWARE_CALLBACK_KEY 0x2000
|
|
#define ADVANCE_VIDEO_CALLBACK_KEY 0x2001
|
|
#define CONFIGURATION_FSC_CALLBACK_KEY 0x2002
|
|
#define CONFIGURATION_RESTORE_FAN_CONTROL_CALLBACK_KEY 0x2003
|
|
#define CONFIGURATION_LVDS_CALLBACK_KEY 0x2004
|
|
#define CONFIGURATION_PREDEFINED_EDID_CALLBACK_KEY 0x2005
|
|
#define ADVANCE_LVDS_CALLBACK_KEY 0x2010
|
|
|
|
//
|
|
// Main Callback Keys. Do not have to be sequential but have to be unique
|
|
//
|
|
#define MAIN_LANGUAGE_CALLBACK_KEY 0x3000
|
|
|
|
//
|
|
// Power Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique
|
|
//
|
|
#define POWER_HARDWARE_CALLBACK_KEY 0x4000
|
|
|
|
//
|
|
// Performance Callback Keys. Do not have to be sequential but have to be unique
|
|
//
|
|
#define PROCESSOR_OVERRIDES_CALLBACK_KEY 0x5000
|
|
#define PERFORMANCE_CALLBACK_KEY 0x5001
|
|
#define BUS_OVERRIDES_CALLBACK_KEY 0x5002
|
|
#define MEMORY_CFG_CALLBACK_KEY 0x5003
|
|
#define PERFORMANCE_STATUS_CALLBACK_KEY 0x5004
|
|
#define MEMORY_RATIO_CALLBACK_KEY 0x5005
|
|
#define MEMORY_MODE_CALLBACK_KEY 0x5006
|
|
|
|
//
|
|
// Security Callback Keys. Do not have to be sequential but have to be unique
|
|
//
|
|
#define SECURITY_SUPERVISOR_CALLBACK_KEY 0x1000
|
|
#define SECURITY_USER_CALLBACK_KEY 0x1001
|
|
#define SECURITY_CLEAR_ALL_CALLBACK_KEY 0x1002
|
|
#define SECURITY_CLEAR_USER_CALLBACK_KEY 0x1004
|
|
#define SECURITY_RESET_AMT_CALLBACK_KEY 0x1008
|
|
#define SECURITY_CHANGE_VT_CALLBACK_KEY 0x1010
|
|
#define SECURITY_MASTER_HDD_CALLBACK_KEY 0x1020
|
|
#define SECURITY_USER_HDD_CALLBACK_KEY 0x1040
|
|
|
|
//
|
|
// Boot Callback Keys. Do not have to be sequential but have to be unique
|
|
//
|
|
#define BOOT_HYPERBOOT_CALLBACK_KEY 0x6003
|
|
#define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE 0x6004
|
|
#define BOOT_HYPERBOOT_CALLBACK_KEY_USB 0x6005
|
|
#define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE_USB_OPT 0x6006
|
|
|
|
//
|
|
// IDCC/Setup FSB Frequency Override Range
|
|
//
|
|
#define EFI_IDCC_FSB_MIN 133
|
|
#define EFI_IDCC_FSB_MAX 240
|
|
#define EFI_IDCC_FSB_STEP 1
|
|
|
|
//
|
|
// Reference voltage
|
|
//
|
|
#define EFI_REF_DAC_MIN 0
|
|
#define EFI_REF_DAC_MAX 255
|
|
#define EFI_GTLREF_DEF 170
|
|
#define EFI_DDRREF_DEF 128
|
|
#define EFI_DIMMREF_DEF 128
|
|
|
|
//
|
|
// Setup FSB Frequency Override Range
|
|
//
|
|
#define EFI_FSB_MIN 133
|
|
#define EFI_FSB_MAX 240
|
|
#define EFI_FSB_STEP 1
|
|
#define EFI_FSB_AUTOMATIC 0
|
|
#define EFI_FSB_MANUAL 1
|
|
#define FSB_FREQ_ENTRY_COUNT ((EFI_FSB_MAX - EFI_FSB_MIN)/EFI_FSB_STEP) + 1
|
|
#define FSB_FREQ_ENTRY_TYPE UINT16_TYPE
|
|
|
|
//
|
|
// Setup processor multiplier range
|
|
//
|
|
#define EFI_PROC_MULT_MIN 5
|
|
#define EFI_PROC_MULT_MAX 40
|
|
#define EFI_PROC_MULT_STEP 1
|
|
#define EFI_PROC_AUTOMATIC 0
|
|
#define EFI_PROC_MANUAL 1
|
|
#define PROC_MULT_ENTRY_COUNT ((EFI_PROC_MULT_MAX - EFI_PROC_MULT_MIN)/EFI_PROC_MULT_STEP) + 1
|
|
#define PROC_MULT_ENTRY_TYPE UINT8_TYPE
|
|
|
|
//
|
|
// PCI Express Definitions
|
|
//
|
|
#define EFI_PCIE_FREQ_DEF 0x0
|
|
|
|
#define PCIE_FREQ_ENTRY_TYPE UINT8_TYPE
|
|
#define PCIE_FREQ_ENTRY_7 0x7
|
|
#define PCIE_FREQ_ENTRY_6 0x6
|
|
#define PCIE_FREQ_ENTRY_5 0x5
|
|
#define PCIE_FREQ_ENTRY_4 0x4
|
|
#define PCIE_FREQ_ENTRY_3 0x3
|
|
#define PCIE_FREQ_ENTRY_2 0x2
|
|
#define PCIE_FREQ_ENTRY_1 0x1
|
|
#define PCIE_FREQ_ENTRY_0 0x0
|
|
|
|
#define PCIE_FREQ_TRANSLATION_TABLE_ENTRIES 8
|
|
#define PCIE_FREQ_TRANSLATION_TABLE { PCIE_FREQ_ENTRY_0, \
|
|
PCIE_FREQ_ENTRY_1, \
|
|
PCIE_FREQ_ENTRY_2, \
|
|
PCIE_FREQ_ENTRY_3, \
|
|
PCIE_FREQ_ENTRY_4, \
|
|
PCIE_FREQ_ENTRY_5, \
|
|
PCIE_FREQ_ENTRY_6, \
|
|
PCIE_FREQ_ENTRY_7 }
|
|
|
|
|
|
#define PCIE_FREQ_PRECISION 2
|
|
#define PCIE_FREQ_VALUE_7 10924
|
|
#define PCIE_FREQ_VALUE_6 10792
|
|
#define PCIE_FREQ_VALUE_5 10660
|
|
#define PCIE_FREQ_VALUE_4 10528
|
|
#define PCIE_FREQ_VALUE_3 10396
|
|
#define PCIE_FREQ_VALUE_2 10264
|
|
#define PCIE_FREQ_VALUE_1 10132
|
|
#define PCIE_FREQ_VALUE_0 10000
|
|
|
|
#define PCIE_FREQ_VALUES { PCIE_FREQ_VALUE_0, \
|
|
PCIE_FREQ_VALUE_1, \
|
|
PCIE_FREQ_VALUE_2, \
|
|
PCIE_FREQ_VALUE_3, \
|
|
PCIE_FREQ_VALUE_4, \
|
|
PCIE_FREQ_VALUE_5, \
|
|
PCIE_FREQ_VALUE_6, \
|
|
PCIE_FREQ_VALUE_7 }
|
|
|
|
//
|
|
// Memory Frequency Definitions
|
|
//
|
|
#define MEMORY_REF_FREQ_ENTRY_DEF 0x08
|
|
|
|
#define MEMORY_REF_FREQ_ENTRY_TYPE UINT8_TYPE
|
|
#define MEMORY_REF_FREQ_ENTRY_3 0x04
|
|
#define MEMORY_REF_FREQ_ENTRY_2 0x00
|
|
#define MEMORY_REF_FREQ_ENTRY_1 0x02
|
|
#define MEMORY_REF_FREQ_ENTRY_0 0x01
|
|
|
|
#define MEMORY_REF_FREQ_TRANSLATION_TABLE_ENTRIES 4
|
|
#define MEMORY_REF_FREQ_TRANSLATION_TABLE { MEMORY_REF_FREQ_ENTRY_0, \
|
|
MEMORY_REF_FREQ_ENTRY_1, \
|
|
MEMORY_REF_FREQ_ENTRY_2, \
|
|
MEMORY_REF_FREQ_ENTRY_3 }
|
|
|
|
#define MEMORY_REF_FREQ_PRECISION 0
|
|
#define MEMORY_REF_FREQ_VALUE_3 333
|
|
#define MEMORY_REF_FREQ_VALUE_2 267
|
|
#define MEMORY_REF_FREQ_VALUE_1 200
|
|
#define MEMORY_REF_FREQ_VALUE_0 133
|
|
|
|
#define MEMORY_REF_FREQ_VALUES { MEMORY_REF_FREQ_VALUE_0, \
|
|
MEMORY_REF_FREQ_VALUE_1, \
|
|
MEMORY_REF_FREQ_VALUE_2, \
|
|
MEMORY_REF_FREQ_VALUE_3 }
|
|
|
|
|
|
//
|
|
// Memory Reference Frequency Definitions
|
|
//
|
|
|
|
#define MEMORY_FREQ_ENTRY_TYPE UINT8_TYPE
|
|
#define MEMORY_FREQ_ENTRY_3 0x4
|
|
#define MEMORY_FREQ_ENTRY_2 0x3
|
|
#define MEMORY_FREQ_ENTRY_1 0x2
|
|
#define MEMORY_FREQ_ENTRY_0 0x1
|
|
|
|
#define MEMORY_FREQ_TRANSLATION_TABLE_ENTRIES 4
|
|
#define MEMORY_FREQ_TRANSLATION_TABLE { MEMORY_FREQ_ENTRY_0, \
|
|
MEMORY_FREQ_ENTRY_1, \
|
|
MEMORY_FREQ_ENTRY_2, \
|
|
MEMORY_FREQ_ENTRY_3 }
|
|
|
|
|
|
#define MEMORY_FREQ_MULT_PRECISION 2
|
|
#define MEMORY_FREQ_MULT_333MHZ_VALUE_3 240
|
|
#define MEMORY_FREQ_MULT_333MHZ_VALUE_2 200
|
|
#define MEMORY_FREQ_MULT_333MHZ_VALUE_1 160
|
|
#define MEMORY_FREQ_MULT_333MHZ_VALUE_0 120
|
|
|
|
#define MEMORY_FREQ_MULT_266MHZ_VALUE_3 300
|
|
#define MEMORY_FREQ_MULT_266MHZ_VALUE_2 250
|
|
#define MEMORY_FREQ_MULT_266MHZ_VALUE_1 200
|
|
#define MEMORY_FREQ_MULT_266MHZ_VALUE_0 150
|
|
|
|
#define MEMORY_FREQ_MULT_200MHZ_VALUE_3 400
|
|
#define MEMORY_FREQ_MULT_200MHZ_VALUE_2 333
|
|
#define MEMORY_FREQ_MULT_200MHZ_VALUE_1 267
|
|
#define MEMORY_FREQ_MULT_200MHZ_VALUE_0 200
|
|
|
|
#define MEMORY_FREQ_MULT_133MHZ_VALUE_3 600
|
|
#define MEMORY_FREQ_MULT_133MHZ_VALUE_2 500
|
|
#define MEMORY_FREQ_MULT_133MHZ_VALUE_1 400
|
|
#define MEMORY_FREQ_MULT_133MHZ_VALUE_0 300
|
|
|
|
#define MEMORY_FREQ_MULT_333MHZ_VALUES { MEMORY_FREQ_MULT_333MHZ_VALUE_0, \
|
|
MEMORY_FREQ_MULT_333MHZ_VALUE_1, \
|
|
MEMORY_FREQ_MULT_333MHZ_VALUE_2, \
|
|
MEMORY_FREQ_MULT_333MHZ_VALUE_3 }
|
|
|
|
#define MEMORY_FREQ_MULT_266MHZ_VALUES { MEMORY_FREQ_MULT_266MHZ_VALUE_0, \
|
|
MEMORY_FREQ_MULT_266MHZ_VALUE_1, \
|
|
MEMORY_FREQ_MULT_266MHZ_VALUE_2, \
|
|
MEMORY_FREQ_MULT_266MHZ_VALUE_3 }
|
|
|
|
#define MEMORY_FREQ_MULT_200MHZ_VALUES { MEMORY_FREQ_MULT_200MHZ_VALUE_0, \
|
|
MEMORY_FREQ_MULT_200MHZ_VALUE_1, \
|
|
MEMORY_FREQ_MULT_200MHZ_VALUE_2, \
|
|
MEMORY_FREQ_MULT_200MHZ_VALUE_3 }
|
|
|
|
#define MEMORY_FREQ_MULT_133MHZ_VALUES { MEMORY_FREQ_MULT_133MHZ_VALUE_0, \
|
|
MEMORY_FREQ_MULT_133MHZ_VALUE_1, \
|
|
MEMORY_FREQ_MULT_133MHZ_VALUE_2, \
|
|
MEMORY_FREQ_MULT_133MHZ_VALUE_3 }
|
|
|
|
//
|
|
// CAS Memory Timing Definitions
|
|
//
|
|
|
|
#define MEMORY_TCL_ENTRY_TYPE UINT8_TYPE
|
|
#define MEMORY_TCL_ENTRY_3 0x2
|
|
#define MEMORY_TCL_ENTRY_2 0x1
|
|
#define MEMORY_TCL_ENTRY_1 0x0
|
|
#define MEMORY_TCL_ENTRY_0 0x3
|
|
|
|
#define MEMORY_TCL_TRANSLATION_TABLE_ENTRIES 4
|
|
#define MEMORY_TCL_TRANSLATION_TABLE { MEMORY_TCL_ENTRY_0, \
|
|
MEMORY_TCL_ENTRY_1, \
|
|
MEMORY_TCL_ENTRY_2, \
|
|
MEMORY_TCL_ENTRY_3 }
|
|
|
|
|
|
#define MEMORY_TCL_PRECISION 0
|
|
#define MEMORY_TCL_VALUE_3 3
|
|
#define MEMORY_TCL_VALUE_2 4
|
|
#define MEMORY_TCL_VALUE_1 5
|
|
#define MEMORY_TCL_VALUE_0 6
|
|
|
|
#define MEMORY_TCL_VALUES { MEMORY_TCL_VALUE_0, \
|
|
MEMORY_TCL_VALUE_1, \
|
|
MEMORY_TCL_VALUE_2, \
|
|
MEMORY_TCL_VALUE_3 }
|
|
|
|
|
|
//
|
|
// TRCD Memory Timing Definitions
|
|
//
|
|
|
|
#define MEMORY_TRCD_ENTRY_TYPE UINT8_TYPE
|
|
#define MEMORY_TRCD_ENTRY_3 0x0
|
|
#define MEMORY_TRCD_ENTRY_2 0x1
|
|
#define MEMORY_TRCD_ENTRY_1 0x2
|
|
#define MEMORY_TRCD_ENTRY_0 0x3
|
|
|
|
#define MEMORY_TRCD_TRANSLATION_TABLE_ENTRIES 4
|
|
#define MEMORY_TRCD_TRANSLATION_TABLE { MEMORY_TRCD_ENTRY_0, \
|
|
MEMORY_TRCD_ENTRY_1, \
|
|
MEMORY_TRCD_ENTRY_2, \
|
|
MEMORY_TRCD_ENTRY_3 }
|
|
|
|
|
|
#define MEMORY_TRCD_PRECISION 0
|
|
#define MEMORY_TRCD_VALUE_3 2
|
|
#define MEMORY_TRCD_VALUE_2 3
|
|
#define MEMORY_TRCD_VALUE_1 4
|
|
#define MEMORY_TRCD_VALUE_0 5
|
|
|
|
#define MEMORY_TRCD_VALUES { MEMORY_TRCD_VALUE_0, \
|
|
MEMORY_TRCD_VALUE_1, \
|
|
MEMORY_TRCD_VALUE_2, \
|
|
MEMORY_TRCD_VALUE_3 }
|
|
|
|
|
|
//
|
|
// TRP Memory Timing Definitions
|
|
//
|
|
|
|
#define MEMORY_TRP_ENTRY_TYPE UINT8_TYPE
|
|
#define MEMORY_TRP_ENTRY_3 0x0
|
|
#define MEMORY_TRP_ENTRY_2 0x1
|
|
#define MEMORY_TRP_ENTRY_1 0x2
|
|
#define MEMORY_TRP_ENTRY_0 0x3
|
|
|
|
#define MEMORY_TRP_TRANSLATION_TABLE_ENTRIES 4
|
|
#define MEMORY_TRP_TRANSLATION_TABLE { MEMORY_TRP_ENTRY_0, \
|
|
MEMORY_TRP_ENTRY_1, \
|
|
MEMORY_TRP_ENTRY_2, \
|
|
MEMORY_TRP_ENTRY_3 }
|
|
|
|
|
|
#define MEMORY_TRP_PRECISION 0
|
|
#define MEMORY_TRP_VALUE_3 2
|
|
#define MEMORY_TRP_VALUE_2 3
|
|
#define MEMORY_TRP_VALUE_1 4
|
|
#define MEMORY_TRP_VALUE_0 5
|
|
|
|
#define MEMORY_TRP_VALUES { MEMORY_TRP_VALUE_0, \
|
|
MEMORY_TRP_VALUE_1, \
|
|
MEMORY_TRP_VALUE_2, \
|
|
MEMORY_TRP_VALUE_3 }
|
|
|
|
|
|
//
|
|
// TRAS Memory Timing Definitions
|
|
//
|
|
#define MEMORY_TRAS_MIN 4
|
|
#define MEMORY_TRAS_MAX 18
|
|
#define MEMORY_TRAS_STEP 1
|
|
#define MEMORY_TRAS_DEFAULT 13
|
|
#define MEMORY_TRAS_COUNT ((MEMORY_TRAS_MAX - MEMORY_TRAS_MIN)/MEMORY_TRAS_STEP) + 1
|
|
#define MEMORY_TRAS_TYPE UINT8_TYPE
|
|
|
|
//
|
|
// Uncore Multiplier Definitions
|
|
//
|
|
#define UCLK_RATIO_MIN 12
|
|
#define UCLK_RATIO_MAX 30
|
|
#define UCLK_RATIO_DEFAULT 20
|
|
|
|
#endif // #ifndef _CONFIGURATION_H
|