mirror of https://github.com/acidanthera/audk.git
212 lines
6.2 KiB
C
212 lines
6.2 KiB
C
/**
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Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@file
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PchRegs.h
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@brief
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Register names for VLV SC.
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values of bits within the registers
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
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- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without <generation_name> inserted.
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**/
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#ifndef _PCH_REGS_H_
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#define _PCH_REGS_H_
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///
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/// Bit Definitions. BUGBUG: drive these definitions to code base. Should not need
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/// to be part of chipset modules
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///
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#ifndef BIT0
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#define BIT0 0x0001
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#define BIT1 0x0002
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#define BIT2 0x0004
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#define BIT3 0x0008
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#define BIT4 0x0010
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#define BIT5 0x0020
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#define BIT6 0x0040
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#define BIT7 0x0080
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#define BIT8 0x0100
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#define BIT9 0x0200
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#define BIT10 0x0400
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#define BIT11 0x0800
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#define BIT12 0x1000
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#define BIT13 0x2000
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#define BIT14 0x4000
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#define BIT15 0x8000
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#define BIT16 0x00010000
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#define BIT17 0x00020000
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#define BIT18 0x00040000
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#define BIT19 0x00080000
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#define BIT20 0x00100000
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#define BIT21 0x00200000
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#define BIT22 0x00400000
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#define BIT23 0x00800000
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#define BIT24 0x01000000
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#define BIT25 0x02000000
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#define BIT26 0x04000000
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#define BIT27 0x08000000
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#define BIT28 0x10000000
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#define BIT29 0x20000000
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#define BIT30 0x40000000
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#define BIT31 0x80000000
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#define BIT32 0x100000000
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#define BIT33 0x200000000
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#define BIT34 0x400000000
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#define BIT35 0x800000000
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#define BIT36 0x1000000000
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#define BIT37 0x2000000000
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#define BIT38 0x4000000000
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#define BIT39 0x8000000000
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#define BIT40 0x10000000000
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#define BIT41 0x20000000000
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#define BIT42 0x40000000000
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#define BIT43 0x80000000000
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#define BIT44 0x100000000000
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#define BIT45 0x200000000000
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#define BIT46 0x400000000000
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#define BIT47 0x800000000000
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#define BIT48 0x1000000000000
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#define BIT49 0x2000000000000
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#define BIT50 0x4000000000000
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#define BIT51 0x8000000000000
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#define BIT52 0x10000000000000
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#define BIT53 0x20000000000000
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#define BIT54 0x40000000000000
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#define BIT55 0x80000000000000
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#define BIT56 0x100000000000000
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#define BIT57 0x200000000000000
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#define BIT58 0x400000000000000
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#define BIT59 0x800000000000000
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#define BIT60 0x1000000000000000
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#define BIT61 0x2000000000000000
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#define BIT62 0x4000000000000000
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#define BIT63 0x8000000000000000
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#endif
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///
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/// The default PCH PCI bus number
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///
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#define DEFAULT_PCI_BUS_NUMBER_PCH 0
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///
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/// Default Vendor ID and Subsystem ID
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///
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#define V_PCH_INTEL_VENDOR_ID 0x8086
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#define V_PCH_DEFAULT_SID 0x7270
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#define V_PCH_DEFAULT_SVID_SID (V_PCH_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID << 16))
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///
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/// Include device register definitions
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///
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#include "PchRegs/PchRegsHda.h"
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#include "PchRegs/PchRegsLpss.h"
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#include "PchRegs/PchRegsPcie.h"
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#include "PchRegs/PchRegsPcu.h"
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#include "PchRegs/PchRegsRcrb.h"
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#include "PchRegs/PchRegsSata.h"
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#include "PchRegs/PchRegsScc.h"
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#include "PchRegs/PchRegsSmbus.h"
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#include "PchRegs/PchRegsSpi.h"
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#include "PchRegs/PchRegsUsb.h"
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//#include "PchRegs/PchRegsLpe.h"
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///
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/// Device IDS that are PCH Server specific
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///
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#define IS_PCH_DEVICE_ID(DeviceId) \
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( \
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(DeviceId == V_PCH_LPC_DEVICE_ID_0) || \
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(DeviceId == V_PCH_LPC_DEVICE_ID_1) || \
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(DeviceId == V_PCH_LPC_DEVICE_ID_2) || \
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(DeviceId == V_PCH_LPC_DEVICE_ID_3) \
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)
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#define IS_PCH_VLV_LPC_DEVICE_ID(DeviceId) \
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( \
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IS_PCH_DEVICE_ID (DeviceId) \
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)
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#define IS_PCH_VLV_SATA_DEVICE_ID(DeviceId) \
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( \
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IS_PCH_VLV_SATA_AHCI_DEVICE_ID (DeviceId) || \
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IS_PCH_VLV_SATA_MODE_DEVICE_ID (DeviceId) || \
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IS_PCH_VLV_SATA_RAID_DEVICE_ID (DeviceId) \
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)
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#define IS_PCH_VLV_SATA_AHCI_DEVICE_ID(DeviceId) \
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( \
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(DeviceId == V_PCH_SATA_DEVICE_ID_D_AHCI) || \
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(DeviceId == V_PCH_SATA_DEVICE_ID_M_AHCI) \
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)
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#define IS_PCH_VLV_SATA_RAID_DEVICE_ID(DeviceId) \
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( \
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(DeviceId == V_PCH_SATA_DEVICE_ID_D_RAID) || \
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(DeviceId == V_PCH_SATA_DEVICE_ID_M_RAID) \
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)
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#define IS_PCH_VLV_SATA_MODE_DEVICE_ID(DeviceId) \
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( \
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(DeviceId == V_PCH_SATA_DEVICE_ID_D_IDE) || \
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(DeviceId == V_PCH_SATA_DEVICE_ID_M_IDE) \
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)
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#define IS_PCH_VLV_USB_DEVICE_ID(DeviceId) \
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( \
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(DeviceId == V_PCH_USB_DEVICE_ID_0) || \
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(DeviceId == V_PCH_USB_DEVICE_ID_1) \
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)
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#define IS_PCH_VLV_PCIE_DEVICE_ID(DeviceId) \
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( \
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(DeviceId == V_PCH_PCIE_DEVICE_ID_0) || \
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(DeviceId == V_PCH_PCIE_DEVICE_ID_1) || \
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(DeviceId == V_PCH_PCIE_DEVICE_ID_2) || \
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(DeviceId == V_PCH_PCIE_DEVICE_ID_3) || \
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(DeviceId == V_PCH_PCIE_DEVICE_ID_4) || \
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(DeviceId == V_PCH_PCIE_DEVICE_ID_5) || \
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(DeviceId == V_PCH_PCIE_DEVICE_ID_6) || \
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(DeviceId == V_PCH_PCIE_DEVICE_ID_7) \
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)
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///
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/// Any device ID that is Valleyview SC
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///
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#define IS_PCH_VLV_DEVICE_ID(DeviceId) \
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( \
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IS_PCH_VLV_LPC_DEVICE_ID (DeviceId) || \
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IS_PCH_VLV_SATA_DEVICE_ID (DeviceId) || \
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IS_PCH_VLV_USB_DEVICE_ID (DeviceId) || \
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IS_PCH_VLV_PCIE_DEVICE_ID (DeviceId) || \
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(DeviceId) == V_PCH_SMBUS_DEVICE_ID || \
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(DeviceId) == V_PCH_HDA_DEVICE_ID_0 || \
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(DeviceId) == V_PCH_HDA_DEVICE_ID_1 \
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)
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#define IS_SUPPORTED_DEVICE_ID(DeviceId) IS_PCH_VLV_DEVICE_ID (DeviceId)
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#endif
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