mirror of https://github.com/acidanthera/audk.git
156 lines
6.6 KiB
C
156 lines
6.6 KiB
C
/** @file
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* Header defining Versatile Express constants (Base addresses, sizes, flags)
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __ARM_VEXPRESS_H__
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#define __ARM_VEXPRESS_H__
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#include <Base.h>
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#include <VExpressMotherBoard.h>
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/***********************************************************************************
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// Platform Memory Map
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************************************************************************************/
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// Can be NOR0, NOR1, DRAM
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#define ARM_VE_REMAP_BASE 0x00000000
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#define ARM_VE_REMAP_SZ SIZE_64MB
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// Motherboard Peripheral and On-chip peripheral
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#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000
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#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ SIZE_256MB
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#define ARM_VE_BOARD_PERIPH_BASE 0x10000000
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#define ARM_VE_CHIP_PERIPH_BASE 0x10020000
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// SMC
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#define ARM_VE_SMC_BASE 0x40000000
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#define ARM_VE_SMC_SZ 0x1C000000
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// NOR Flash 1
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#define ARM_VE_SMB_NOR0_BASE 0x40000000
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#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
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// NOR Flash 2
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#define ARM_VE_SMB_NOR1_BASE 0x44000000
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#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
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// SRAM
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#define ARM_VE_SMB_SRAM_BASE 0x48000000
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#define ARM_VE_SMB_SRAM_SZ SIZE_32MB
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// USB, Ethernet, VRAM
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#define ARM_VE_SMB_PERIPH_BASE 0x4C000000
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#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
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#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB
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// DRAM
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#define ARM_VE_DRAM_BASE 0x60000000
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#define ARM_VE_DRAM_SZ 0x40000000
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// Inside the DRAM we allocate a section for the VRAM (Video RAM)
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#define LCD_VRAM_CORE_TILE_BASE 0x64000000
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// External AXI between daughterboards (Logic Tile)
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#define ARM_VE_EXT_AXI_BASE 0xE0000000
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#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */
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/***********************************************************************************
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Core Tile memory-mapped Peripherals
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************************************************************************************/
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// PL111 Colour LCD Controller - core tile
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#define PL111_CLCD_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x20000)
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// PL341 Dynamic Memory Controller Base
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#define ARM_VE_DMC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE0000)
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// PL354 Static Memory Controller Base
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#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)
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// System Configuration Controller register Base addresses
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//#define ARM_VE_SYS_CFG_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
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#define ARM_VE_SYS_CFGRW0_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
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#define ARM_VE_SYS_CFGRW1_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2004)
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#define ARM_VE_SYS_CFGRW2_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2008)
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#define ARM_PLATFORM_SCC_BASE ARM_VE_SYS_CFGRW0_REG
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// SP805 Watchdog on Cortex A9 core tile
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#define SP805_WDOG_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE5000)
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// BP147 TZPC Base Address
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#define ARM_VE_TZPC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE6000)
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// PL301 Fast AXI Base Address
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#define ARM_VE_FAXI_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE9000)
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// TZASC Trust Zone Address Space Controller Base Address
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#define ARM_VE_TZASC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xEC000)
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// PL310 L2x0 Cache Controller Base Address
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//#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000
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/***********************************************************************************
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Select between Motherboard and Core Tile peripherals
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************************************************************************************/
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// Specify which PL111 to use
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//#define PL111_CLCD_BASE PL111_CLCD_MOTHERBOARD_BASE
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#define PL111_CLCD_BASE PL111_CLCD_CORE_TILE_BASE
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// Specify which Watchdog to use
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#define SP805_WDOG_BASE SP805_WDOG_MOTHERBOARD_BASE
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//#define SP805_WDOG_BASE SP805_WDOG_CORE_TILE_BASE
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/***********************************************************************************
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Peripherals' misc settings
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************************************************************************************/
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#define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK 0x2000
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#define ARM_VE_CFGRW1_REMAP_NOR0 0
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#define ARM_VE_CFGRW1_REMAP_NOR1 (1 << 28)
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#define ARM_VE_CFGRW1_REMAP_EXT_AXI (1 << 29)
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#define ARM_VE_CFGRW1_REMAP_DRAM (1 << 30)
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// TZASC - Other settings
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#define ARM_VE_DECPROT_BIT_TZPC (1 << 6)
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#define ARM_VE_DECPROT_BIT_DMC_TZASC (1 << 11)
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#define ARM_VE_DECPROT_BIT_NMC_TZASC (1 << 12)
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#define ARM_VE_DECPROT_BIT_SMC_TZASC (1 << 13)
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#define ARM_VE_DECPROT_BIT_EXT_MAST_TZ (1)
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#define ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK (1 << 3)
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#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK (1 << 4)
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#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)
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// PL031 RTC - Other settings
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#define PL031_PPM_ACCURACY 300000000
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// SP805 Watchdog - Other settings
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#define SP805_CLOCK_FREQUENCY 32000
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#define SP805_MAX_TICKS 0xFFFFFFFF
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// PL111 Lcd
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#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
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/***********************************************************************************
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// EFI Memory Map in Permanent Memory (DRAM)
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************************************************************************************/
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// This region is allocated at the bottom of the DRAM. It will be used
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// for fixed address allocations such as Vector Table
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#define ARM_VE_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB
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// This region is the memory declared to PEI as permanent memory for PEI
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// and DXE. EFI stacks and heaps will be declared in this region.
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#define ARM_VE_EFI_MEMORY_REGION_SZ SIZE_256MB
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#endif
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